Encoding:

EXTEND

11110

00000

0

HWR

SHIFT

00110

000

ry

sel = 3

SLL

00

5

5

1

5

5

3

3

3

2

Format: 

RDHWR ry,HWR

MIPS16e2

Read Hardware Register Extended

Purpose:

Read Hardware Register Extended

To move the contents of a hardware register to a general purpose register (GPR) if that operation is enabled by privileged software.

The purpose of this instruction is to give user mode access to specific information that is otherwise only visible in kernel mode.

Description: 

 GPR[ry] = HWR[HWR]

If access is allowed to the specified hardware register, the contents of the register specified by SHIFT is loaded into general register ry Access control for each register is selected by the bits in the coprocessor 0 HWREna register.

The available hardware registers, and the encoding of the rd field for each, are shown below.

RDHWR Register Numbers

Register Number

(HWR Value)

Mnemonic

Description

0

CPUNum

Number of the CPU on which the program is currently running. This register provides read access to the coprocessor 0 EBaseCPUNum field.

1

SYNCI_Step

Address step size to be used with the SYNCI instruction, or zero if no caches need be synchronized. See that instruction's description for the use of this value.

2

CC

High-resolution cycle counter. This register provides read access to the coprocessor 0 Count Register.

3

CCRes

Resolution of the CC register. This value denotes the number of cycles between update of the register. For example:

CCRes ValueMeaning

1CC register increments every CPU cycle 2CC register increments every second CPU cycle 3CC register increments every third CPU cycle etc.

4

Rsv

Reserved.

5

XNP

Indicates support for Release 6 Double-Width LLX/SCX family of instructions. If set to 1, then LLX/SCX family of instructions is not present, otherwise present in the implementation. In absence of hardware support for double-width or extended atomics, user software may emulate the instruction's behavior through other means. See Config5XNP.

6-28

These registers numbers are reserved for future architecture use. Access results in a Reserved Instruction Exception.

29

ULR

User Local Register. This register provides read access to the coprocessor 0 UserLocal register, if it is implemented. In some operating environments, the UserLocal register is a pointer to a thread-specific storage block.

30-31

These register numbers are reserved for implementation-dependent use. If they are not implemented, access results in a Reserved Instruction Exception.

Restrictions:

Unpredictable prior to MIPS16e2. Access to the specified hardware register is enabled if Coprocessor 0 is enabled, or if the corresponding bit is set in the HWREna register. If access is not allowed or the register is not implemented, a

Reserved Instruction Exception is signaled.

Operation: 

case HWR
   0: temp = EBaseCPUNum
   1: temp = SYNCI_StepSize()
   2: temp = Count
   3: temp = CountResolution()
   5: temp = XNP
   29: temp = UserLocal 
   30: temp = Implementation-Dependent-Value
   31: temp = Implementation-Dependent-Value
   otherwise: SignalException(ReservedInstruction)
endcase
GPR[Xlat[ry]] = temp

Exceptions:

Reserved Instruction