Encoding:

Format:

MTC0 ry, r32, sel

Purpose:

Move to Coprocessor 0 Extended

To move the contents of a general register to a coprocessor 0 register.

Description:

 CPR[0, r32, sel] = GPR[ry]

The contents of general register ry are loaded into the coprocessor 0 register specified by the combination of r32 and

sel. Not all coprocessor 0 registers support the sel field. In those instances, the sel field must be set to zero.

Restrictions:

Unpredictable prior to MIPS16e2. The results are UNDEFINED if coprocessor 0 does not contain a register as specified by r32 and sel.

Operation:

data = GPR[XLat[ry]]
reg = r32
if IsCoprocessorRegisterImplemented (0, reg, sel) then
   CPR[0,reg,sel] = data
         if (Config5MVH = 1) then
             // The most-significant bit may vary by register. Only supported
             // bits should be written 0. Extended LLAddr is not written with 0s,
             // as it is a read-only register. BadVAddr is not written with 0s, as
             // it is read-only
             if (Config3LPA = 1) then
                if (reg,sel = EntryLo0 or EntryLo1) then CPR[0,reg,sel]63:32 = 032
                if (reg,sel = MAAR) then CPR[0,reg,sel]63:32 = 032 endif
                   // TagLo is zeroed only if the implementation-dependent bits
                   // are writeable
                if (reg,sel = TagLo) then CPR[0,reg,sel]63:32 = 032 endif
                if (Config3VZ = 1) then 
                   if (reg,sel = EntryHi) then CPR[0,reg,sel]63:32 = 032 endif
                endif
          endif
   endif
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction