Encoding:

Format:

LWR rx, immediate(rb)

Purpose:

Load Word Right Extended

To load the least-significant part of a word as a signed value from an unaligned memory address

Description:

GPR[rx] = GPR[rx] MERGE memory[GPR[rb] + immediate]

The 9-bit signedimmediate value is added to the contents of GPR rb to form an effictive address (EffAddr).

Restrictions:

Unpredictable prior to MIPS16e2.

Operation:

vAddr = sign_extend(immediate) + GPR[XLat[rb]]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..2 || (pAddr1..0 xor ReverseEndian2)
if BigEndianMem = 0 then
   pAddr = pAddrPSIZE-1..2 || 02
endif
byte = vAddr1..0 xor BigEndianCPU2
memword = LoadMemory (CCA, byte, pAddr, vAddr, DATA)
temp = memword31..32-8*byte || GPR[XLat[rx]]31-8*byte..0
GPR[XLat[rx]] = temp

Exceptions:

TLB Refill, TLB Invalid, Bus Error, Address Error, Watch

Programming Notes:

The architecture provides no direct support for treating unaligned words as unsigned values, that is, zeroing bits

63..32 of the destination register when bit 31 is loaded.

Historical Information:

In the MIPS I architecture, the LWL and LWR instructions were exceptions to the load-delay scheduling restriction.

A LWL or LWR instruction which was immediately followed by another LWL or LWR instruction, and used the same destination register would correctly merge the 1 to 4 loaded bytes with the data loaded by the previous instruction. All such restrictions were removed from the architecture in MIPS II.