Encoding:

Format:

LL rx, immediate(rb)

Purpose:

Load Linked Word Immediate

To load a word from memory for an atomic read-modify-write.

Description:

 GPR[rx] = memory[GPR[rb] + immediate]

The LL and SC instructions provide the primitives to implement atomic read-modify-write (RMW) operations for synchronizable memory locations.

The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched and written into GPR rx. The 9-bit signed immediate value is added to the contents of GPR rb to form an effective address.

This begins a RMW sequence on the current processor. There can be only one active RMW sequence per processor.

When an LL is executed it starts an active RMW sequence replacing any other sequence that was active. The RMW sequence is completed by a subsequent SC instruction that either completes the RMW sequence atomically and succeeds, or does not and fails.

Executing LL on one processor does not cause an action that, by itself, causes an SC for the same block to fail on another processor.

An execution of LL does not have to be followed by execution of SC; a program is free to abandon the RMW sequence without attempting a write.

Restrictions:

Unpredictable prior to MIPS16e2. The addressed location must be synchronizable by all processors and I/O devices sharing the location; if it is not, the result is UNPREDICTABLE. Which storage is synchronizable is a function of both CPU and system implementations. See the documentation of the SC instruction for the formal definition.

The effective address must be naturally-aligned. If either of the 2 least-significant bits of the effective address is nonzero, an Address Error exception occurs.

Operation:

vAddr = sign_extend(immediate) + GPR[XLat[rb]]
if vAddr1..0 != 02 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
memword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
GPR[XLat[rx]]= memword
LLbit = 1

Exceptions:

TLB Refill, TLB Invalid, Address Error, Watch

Programming Notes:

MIPS16e2 implements a 9-bit immediate value as the offset.