EXTEND 11110 |
CP0 000 |
sel[2:0] 001 |
SETBIT_NORES 00111 |
I8 01100 |
MOVR32 111 |
000 |
00000 |
EXTEND 11110 |
CP0 000 |
sel[2:0] 001 |
SETBIT 00011 |
I8 01100 |
MOVR32 111 |
ry |
00000 |
5 |
3 |
3 |
5 |
5 |
3 |
3 |
5 |
EVPE |
MIPS16e2 |
Enable Virtual Processor Execution Extended |
EVPE ry |
MIPS16e2 |
Enable Virtual Processor Execution Extended |
Enable Virtual Processor Execution Extended
To return the previous value of the MVPControl register and enable multi-VPE execution. If EVPE is specified without an argument, GPR r0 is implied, which discards the previous value of the MVPControl register.
GPR[ry] = MVPControl; MVPControlEVP = 1
The current value of the MVPControl register isloaded into general register ry. The Enable Virtual Processors (EVP) bit in the MVPControl register is then set, enabling concurrent execution of instruction streams on all non-inhibited
Virtual Processing Elements (VPEs) on a processor.
Unpredictable prior to MIPS16e2. If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled. If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the
EVP bit is unchanged by the instruction.
In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.
Operation - EVPE:
The following operation pertains to the EVPE instruction.
if(VPEConf0MVP = 1) then MVPControlEVP = 1 endif
Operation - EVPE ry:
The following operation pertains to the EVPE ry instruction.
data = MVPControl GPR[XLat[ry]] = data if(VPEConf0MVP = 1) then MVPControlEVP = 1 endif
Coprocessor Unusable
Reserved Instruction (Implementations that do not include the MT Module)
The effects of this instruction are identical to those accomplished by the sequence of reading MVPControl into a GPR, setting the EVP bit to create a temporary value in a second GPR, and writing that value back to MVPControl. Unlike the multiple instruction sequence, however, the EVPE instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception, nor by the scheduling of a different instruction stream.
If an EVPE instruction is followed in the same instruction stream by an MFC0 or MFTR from the MVPControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the EVPE and the read of MVPControl to guarantee that the new state of EVP will be accessed by the read.