Encoding:

Format:

DVPE 

DVPE ry

Purpose:

Disable Virtual Processor Execution Extended

To return the previous value of the MVPControl register and disable multi-VPE execution. If DVPE is specified without an argument, GPR r0 is implied, which discards the previous value of the MVPControl register.

Description:

GPR[ry] = MVPControl; MVPControlEVP = 0

The current value of the MVPControl register isloaded into general register ry. The Enable Virtual Processors (EVP) bit in the MVPControl register is then cleared, suspending concurrent execution of instruction streams other than the instruction stream that issues the DVPE.

Restrictions:

Unpredictable prior to MIPS16e2. If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled. If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the

EVP bit is unchanged by the instruction.

In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception.

Operation - DVPE:

The following operation pertains to the DVPE instruction.

if(VPEConf0MVP = 0) then
MVPControlEVP = 0
endif

Operation - DVPE ry:

The following operation pertains to the DVPE ry instruction.

data = MVPControl
GPR[XLat[ry]] = data
if(VPEConf0MVP = 0) then
MVPControlEVP = 0
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction (Implementations that do not include the MT Module)

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading MVPControl into a GPR, clearing the EVP bit to create a temporary value in a second GPR, and writing that value back to MVPControl. Unlike the multiple instruction sequence, however, the DVPE instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception, nor by the scheduling of a different instruction stream.

The effect of a DVPE instruction may not be instantaneous. An instruction hazard barrier, e.g., JR.HB, is required to guarantee that all other TCs have been suspended.

If a DVPE instruction is followed in the same instruction stream by an MFC0 or MFTR from the MVPControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the DVPE and the read of MVPControl to guarantee that the new state of EVP will be accessed by the read.