Encoding:

EXTEND

11110

CP0

000

sel[2:0]

001

CLRBIT_NORES

00110

I8

01100

MOVR32

111

000

00001

EXTEND

11110

CP0

000

sel[2:0]

001

CLRBIT

00010

I8

01100

MOVR32

111

ry

00001

5

3

3

5

5

3

3

5

Format:

DMT 

MIPS16e2

Disable Multi-Threaded Execution Extended

DMT ry

MIPS16e2

Disable Multi-Threaded Execution Extended

Purpose:

Disable Multi-Threaded Execution Extended

To return the previous value of the VPEControl register and disable multi-threaded execution. If DMT is specified without an argument, GPR r0 is implied, which discards the previous value of the VPEControl register.

Description:

GPR[ry] = VPEControl; VPEControlTE = 0

The current value of the VPEControl register isloaded into general register ry. The Threads Enable (TE) bit in the

VPEControl register is then cleared, suspending concurrent execution of instruction streams other than that which

issues the DMT. This is independent of any per-TC halted state.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

In implementations that do not implement the MT Module, this instruction results in a Reserved Instruction Exception. Unpredictable prior to MIPS16e2.

Operation - DMT:

The following operation pertains to the DMT instruction.

VPEControlTE = 0

Operation - DMT ry:

The following operation pertains to the DMT ry instruction.

data = VPEControl
GPR[XLat[ry]] = sign_extend(data)
VPEControlTE = 0

Exceptions:

Coprocessor Unusable

Reserved Instruction (Implementations that do not include the MT Module)

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading VPEControl into a GPR, clearing the TE bit to create a temporary value in a second GPR, and writing that value back to VPEControl. Unlike the multiple instruction sequence, however, the DMT instruction does not consume a temporary register, and cannot be aborted by an interrupt or exception.

The effect of a DMT instruction may not be instantaneous. An instruction hazard barrier, e.g., JR.HB, is required to guarantee that all other threads have been suspended. If a DMT instruction is followed in the same instruction stream by an MFC0 or MFTR from the VPEControl register, a JALR.HB, JR.HB, EHB, or ERET instruction must be issued between the DMT and the read of VPEControl to guarantee that the new state of TE will be accessed by the read.