Encoding:

Format:

DI 

DI ry

Purpose:

Disable Interrupts Extended

To return the previous value of the Status register and disable interrupts. If DI is specified without an argument, GPR r0 is implied, which discards the previous value of the Status register.

Description:

 GPR[ry] = Status; StatusIE = 0

The current value of the Status register is loaded into general register ry. The Interrupt Enable (IE) bit in the Status register is then cleared.

Restrictions:

Unpredictable prior to MIPS16e2. If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Operation - DI:

The following operation pertains to the DI instruction.

StatusIE = 0

Operation - DI ry:

The following operation pertains to the DI ry instruction.

data = Status
GPR[XLat[ry]] = data
StatusIE = 0

Exceptions:

Coprocessor Unusable

Programming Notes:

The effects of this instruction are identical to those accomplished by the sequence of reading Status into a GPR, clearing the IE bit, and writing the result back to Status. Unlike the multiple instruction sequence, however, the DI instruction cannot be aborted in the middle by an interrupt or exception.

This instruction creates an execution hazard between the change to the Status register and the point where the change to the interrupt enable takes effect. This hazard is cleared by the EHB, JALR.HB, JR.HB, or ERET instructions. Software must not assume that a fixed latency will clear the execution hazard.