RR 11101 |
rx |
ry |
MULTU 11001 |
5 |
3 |
3 |
5 |
MULTU rx, ry |
MIPS16e |
Multiply Unsigned Word |
Multiply Unsigned Word
To multiply 32-bit unsigned integers.
(LO, HI) = GPR[rx] * GPR[ry]
The 32-bit word value in GPR rx is multiplied by the 32-bit value in GPR ry, treating both operands as unsigned values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the highorder 32-bit word is placed into special register HI.
No arithmetic exception occurs under any circumstances.
None
prod = (0 || GPR[Xlat(rx)]) * (0 || GPR[Xlat(ry)]) LO = sign_extend(prod31..0) HI = sign_extend(prod63..32)
None
In some processors the integer multiply operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an opportunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel.
Programs that require overfl w detection must check for it explicitly.
Where the size of the operands are known, software should place the shorter operand in GPR rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.