|
RR 11101 |
000 |
nd 0 |
l 0 |
ra 1 |
J(AL)R(C) 00000 |
|
5 |
3 |
1 |
1 |
1 |
5 |
JR ra |
MIPS16e |
Jump Register Through Register ra |
To execute a branch to the instruction address in the return address register.
PC = GPR[ra]
The program unconditionally jumps to the address specifiein GPR 31, with a delay of one instruction. The instruction sets the ISA Mode bit to the value in GPR 31 bit 0.
Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.
The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.
The effective target address in GPR 31 must be naturally-aligned. If bit 0 is zero and bit 1 is one,then an Address
Error exception occurs when the jump target is subsequently fetched as an instruction.
An extended instruction should not be placed in a jump delay slot, because this causes one-half of an instruction to be executed.
Processor operation is UNPREDICTABLE if a branch or jump instruction is placed in the delay slot of a jump.
I+1: PC = GPR[31]GPRLEN-1..1 || 0
ISAMode = GPR[31]0
None