|
RR 11101 |
rx |
nd 1 |
l 0 |
ra 0 |
J(AL)R(C) 00000 |
|
5 |
3 |
1 |
1 |
1 |
5 |
JRC rx |
MIPS16e |
Jump Register Through MIPS16e GPR, Compact |
To execute a branch to an instruction address in a register
PC = GPR[rx]
The program unconditionally jumps to the address specifiein GPR rx, with no delay slot instruction. The instruction sets the ISA Mode bit to the value in GPR rx bit 0.
Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.
The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.
The effective target address in GPR rx must be naturally-aligned. If bit 0 is zero and bit 1 is one,then an Address
Error exception occurs when the jump target is subsequently fetched as an instruction.
I: PC = GPR[Xlat(rx)]GPRLEN-1..1 || 0 ISAMode = GPR[Xlat(rx)]0
None.
Unlike most MIPS "jump" instructions, JRC does not have a delay slot.