Encoding:

Format:

JAL target

Purpose:

To execute a procedure call within the current 256 MB-aligned region and preserve the current ISA.

Description:

Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, at which location execution continues after a procedure call. The value stored in GPR 31 bit 0 reflect the current value of the ISA Mode bit.

This is a PC-region branch (not PC-relative);the effective target address is in the "current" 256 MB-aligned region.

The low 28 bits of the target address is the target fielshifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself).

Jump to the effective target address, preserving the ISA Mode bit. Execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself.

The opcode fieldescribes a generaljump-and-link operation, with the x fielas a variable. The individualinstructions, JAL and JALX have specific alues for this variables.

Restrictions:

An extended instruction should not be placed in a jump delay slot as it causes one-half of an instruction to be executed.

Processor operation is UNPREDICTABLE if a branch or jump instruction is placed in the delay slot of a jump.

Operation:

I:    GPR[31] = (PC + 6)GPRLEN-1..1 || ISAMode
I+1:  PC = PCGPRLEN-1..28 || target || 02

Exceptions:

None

Programming Notes:

Forming the jump target address by catenating PC and the 26-bittarget address rather than adding a signed offsetto the PC is an advantage if all program code addresses fi into a 256 MB region aligned on a 256 MB boundary.

It allows a branch from anywhere in the region to anywhere in the region, an action not allowed by a signed relative offset.

This definitiocreates the boundary case where the jump instruction is in the last word of a 256 MB region and can therefore jump only to the following 256 MB region containing the jump delay slot.