Encoding:

Format:

JALX target

Purpose:

To execute a procedure call within the current 256 MB-aligned region and change the ISA Mode from 32-bit MIPS to

MIPS16e.

Description:

Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, at which location execution continues after a procedure call. The value stored in GPR 31 bit 0 reflect the current value of the ISA Mode bit.

This is a PC-region branch (not PC-relative);the effective target address is in the "current" 256 MB-aligned region.

The low 28 bits of the target address is the instr_index fielshifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself).

Jump to the effective target address,toggling the ISA Mode bit. Execute the instruction that follows the jump,in the branch delay slot, before executing the jump itself.

Restrictions:

Processor operation is UNPREDICTABLE if a branch,jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.

Operation:

I:    GPR[31] = PC + 8
I+1:  PC = PCGPRLEN..28 || instr_index || 02
      ISAMode = (not ISAMode)

Exceptions:

None

Programming Notes:

Forming the branch target address by catenating PC and index bits rather than adding a signed offset to the PC is an advantage if all program code addresses fi into a 256 MB region aligned on a 256 MB boundary. It allows a branch from anywhere in the region to anywhere in the region, an action not allowed by a signed relative offset.

This definitiocreates the following boundary case: When the branch instruction is in the last word of a 256 MB region, it can branch only to the following 256 MB region containing the branch delay slot.