|
RR 11101 |
rx |
nd 0 |
l 1 |
ra 0 |
J(AL)R(C) 00000 |
|
5 |
3 |
1 |
1 |
1 |
5 |
JALR ra, rx |
MIPS16e |
Jump and Link Register |
To execute a procedure call to an instruction address in a register.
GPR[ra] = return_addr, PC = GPR[rx]
The program unconditionally jumps to the address contained in GPR rx, with a delay of one instruction. The instruction sets the ISA Mode bit to the value in GPR rx bit 0.
The address ofthe instruction following the delay slotis placed into GPR 31. The value stored in GPR 31 bit 0 reflects the current alue of the ISA Mode bit.
Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.
The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.
The effective target address in GPR rx must be naturally-aligned. If bit 0 is zero and bit 1 is one, an Address Error exception occurs when the jump target is subsequently fetched as an instruction.
An extended instruction should not be placed in a jump delay slot, because this causes one-half of an instruction to be executed.
Processor operation is UNPREDICTABLE if a branch or jump instruction is placed in the delay slot of a jump.
I: GPR[31] = (PC + 4)GPRLEN-1..1 || ISAMode
I+1: PC = GPR[Xlat(rx)]GPRLEN-1..1 || 0
ISAMode = GPR[Xlat(rx)]0
None