Encoding:

RR

11101

rx

nd

1

l

1

ra

0

J(AL)R(C)

00000

5

3

1

1

1

5

Format: 

JALRC ra, rx

MIPS16e

Jump and Link Register, Compact

Purpose:

To execute a procedure call to an instruction address in a register

Description: 

 GPR[ra] = return_addr, PC = GPR[rx]

The program unconditionally jumps to the address contained in GPR rx, with no delay slotinstruction. The instruction sets the ISA Mode bit to the value in GPR rx bit 0.

The address of the instruction following the jump is placed into GPR 31. The value stored in GPR 31 bit 0 reflectthe current value of the ISA Mode bit.

Bit 0 of the target address is always zero so that no Address Exceptions occur when bit 0 of the source register is one.

The opcode and function fieldescribe a generaljump-thru-register operation, with the nd (no delay slot),l (link), and ra (source register is ra) fieldas variables. The individual instructions, JALR, JR, JALRC, and JRC have specifi values for these variables.

Restrictions:

The effective target address in GPR rx must be naturally-aligned. If bit 0 is zero and bit 1 is one, an Address Error exception occurs when the jump target is subsequently fetched as an instruction.

Operation: 

I:    GPR[31] = (PC + 2)GPRLEN-1..1 || ISAMode
      PC = GPR[Xlat(rx)]GPRLEN-1..1 || 0
      ISAMode = GPR[Xlat(rx)]0

Exceptions:

None.

Programming Notes:

Unlike most "jump" instructions in the MIPS instruction set, JALRC does not have a delay slot.