Encoding:

Format:

DIV rx, ry

Purpose:

Divide Word

To divide 32-bit signed integers.

Description:

 (LO, HI) = GPR[rx] / GPR[ry]

The 32-bit word value in GPR rx is divided by the 32-bit value in GPR ry,treating both operands as signed values.

The 32-bit quotient is placed into special register LO, and the 32-bit remainder is placed into special register HI.

No arithmetic exception occurs under any circumstances.

Restrictions:

If the divisor in GPR ry is zero, the arithmetic result is UNPREDICTABLE.

Operation:

q = GPR[Xlat(rx)] div GPR[Xlat(ry)]
r = GPR[Xlat(rx)] mod GPR[Xlat(ry)]
LO = q
HI = r

Exceptions:

None

Programming Notes:

No arithmetic exception occurs under any circumstances. If divide-by-zero or overfl w conditions are detected and some action taken, then the divide instruction is typically followed by additional instructions to check for a zero divisor and/or for overfl w.

Ifthe divide is asynchronous then the zero-divisor check can execute in parallel with the divide. The action taken on either divide-by-zero or overfl w is either a convention within the program itself, or more typically within the system software; one possibility is to take a BREAK exception with a code fiel value to signal the problem to the system software.

As an example,the C programming language in a UNIX® environment expects division by zero to either terminate the program or execute a program-specifie signal handler. C does not expect overfl w to cause any exceptional condition. If the C compiler uses a divide instruction, it also emits code to test for a zero divisor and execute a BREAK instruction to inform the operating system if a zero is detected.

Where the size of the operands are known, software should place the shorter operand in GPR ry. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.

In some processors the integer divide operation may proceed asynchronously and allow other CPU instructions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an opportunity for performance improvement by scheduling the divide so that other instructions can execute in parallel.

Historical Perspective:

In MIPS 1 through MIPS III, if either of the two instructions preceding the divide is an MFHI or MFLO, the result of the MFHI or MFLO is UNPREDICTABLE. Reads of the HI or LO special register must be separated from subsequent instructions that write to them by two or more instructions. This restriction was removed in MIPS IV and

MIPS32 and all subsequent levels of the architecture.