Encoding:

COP0

010000

00011

001

00000

sel

Format:

DMFGC0 rt, rd, sel

MIPS64

Doubleword Move from Guest Coprocessor 0

Purpose:

Doubleword Move from Guest Coprocessor 0

To move the contents of a guest coprocessor 0 register to a general purpose register (GPR).

Description:

 GPR[rt] = CPR[0,rd,sel]

The contents of the guest context coprocessor 0 register are loaded into GPR rt. Note that not all guest context coprocessor 0 registers support the sel ield. In those instances, the sel ield must be zero.

Restrictions:

The results are UNDEFINED if the guest context coprocessor 0 does not contain a register as speciied by rd and sel, or if the guest context coprocessor 0 register speciied by rd and sel is a 32-bit register.

The guest context does not implement the Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled. If access to Coprocessor 0 is enabled but access to 64-bit operations is not enabled, a Reserved Instruction Exception is signaled.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3_VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   if(not Are64bitOperationsEnabled()) then
      SignalException(ReservedInstruction)
   endif
   datadoubleword = Guest.CPR[0,rd,sel]
   GPR[rt] = datadoubleword
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

00011

011

00000

sel

Format:

DMTGC0 rt, rd, sel

MIPS64

Doubleword Move to Guest Coprocessor 0

Purpose:

Doubleword Move to Guest Coprocessor 0

To move a doubleword from a GPR to a guest context coprocessor 0 register.

Description:

 CPR[0,rd,sel] = GPR[rt]

The contents of GPR rt are loaded into the guest context coprocessor 0 register speciied in the rd and sel ields. Note that not all guest context coprocessor 0 registers support the sel ield. In those instances, the sel ield must be zero.

Restrictions:

The results are UNDEFINED if guest context coprocessor 0 does not contain a register as speciied by rd and sel, or if the guest context coprocessor 0 register speciied by rd and sel is a 32-bit register or the destination register is the

Guest.Count register.

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3_VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   if(not Are64bitOperationsEnabled()) then
      SignalException(ReservedInstruction)
   endif
   datadoubleword = GPR[rt]
   CPR[0,rd,sel] = datadoubleword
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

00011

000

00000

sel

Format:

MFGC0 rt, rd, sel

MIPS32

Move from Guest Coprocessor 0

Purpose:

Move from Guest Coprocessor 0

To move the contents of a guest coprocessor 0 register to a general register.

Description:

 GPR[rt] = Guest.CPR[0, rd, sel]

The contents of the guest context coprocessor 0 register speciied by the combination of rd and sel are sign-extended and loaded into general register rt. Note that not all guest context coprocessor 0 registers support the sel ield. In those instances, the sel ield must be zero.

When the guest context coprocessor 0 register speciied is the EntryLo0 or the EntryLo1 register, the RI/XI ields appear at bits 31:30 of the destination register. This feature supports 32-bit addressing mode compatibility on a

MIPS64 system.

Restrictions:

The results are UNDEFINED if the guest context coprocessor 0 does not contain the register speciied by rd and sel.

The guest context does not implement the Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

MFGC0 must behave exactly the same as the corresponding guest MFC0instruction, exceptthatit will not cause exceptions that are speciic to guest, such as GPSI and GSFC. Speciically, if the guest register is replicated in guest context, then the read will return the register value, if the register is Reserved for Architecture/Implementation or is

Not Available,the read returns 0,ifthe registeris Shared (such as WatchHi)then the read will always return the register value except that ields invisible to guest are zeroed out.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3_VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   reg = rd
   data = Guest.CPR[0,reg,sel]
   if (reg,sel = EntryLo1 or reg,sel = EntryLo0 then
      GPR[rt]_29..0= data_29..0
      GPR[rt]₃₁= data₆₃
      GPR[rt]₃₀= data₆₂
      GPR[rt]_63..32= sign_extend(data₆₃)
   else
      GPR[rt] = sign_extend(data)
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

00011

100

00000

sel

Format:

MFHGC0 rt, rd, sel

MIPS32 Release 5

Move from High Guest Coprocessor 0

Purpose:

Move from High Guest Coprocessor 0

To move the contents of the upper 32-bits of a guest coprocessor 0 register, extended by 32-bits, to a general register.

Description:

 GPR[rt] = Guest.CPR[0,rd,sel][63:32]

The contents ofthe guest coprocessor 0 register speciied by the combination of rd and sel are sign-extended and loaded into general register rt. Note that not all coprocessor 0 registers support the sel ield. In those instances, the sel ield must be zero.

When the coprocessor 0 register speciied is the EntryLo0 or the EntryLo1 register, MFHGC0 must undo the effects of MTHGC0. That is, bits 31:30 of the register must be returned as bits 1:0 of the GPR, and bits 32 and those of greater signiicance must be left shifted by 2 and written to bits 31:2 of the GPR.

This feature supports MIPS32 backward compatability on a MIPS64 system.

Restrictions:

The results are UNDEFINED if guest coprocessor 0 does not contain a register as speciied by rd and sel, or the register exists but is not extended by 32-bits, or the register is extended for XPA, but XPA is not enabled. XPA is a

Release 5 feature.

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

MFHGC0 must behave exactly the same as the corresponding guest MFHC0instruction, exceptthatit will not cause exceptions that are speciic to guest, such as GPSI and GSFC. Speciically, if the guest register is replicated in guest context, then the read will return the register value, if the register is Reserved for Architecture/Implementation or is

Not Available,the read returns 0,if the registeris Shared (e.g., WatchHi, butitis not extended)then the read will always return the register value except that ields invisible to guest are zeroed out.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Operation:

PABITS isthe total number of physical address bitsimplemented. The term can be found in the deinition of

EntryLo0 and EntryLo1.

if IsCoprocessorEnabled(0) then
   reg = rd
   data = Guest.CPR[0,reg,sel]
   if (reg,sel = EntryLo1 or reg,sel = EntryLo0) then
      if (Root.Config3_LPA = 1 and Root.PageGrain_ELPA = 1) then // PABITS > 36
         GPR[rt]_31:0= data_61..30
         GPR[rt]_63..32= (data₆₁)³²// sign-extend
      endif
   else
      GPR[rt] = sign_extend(data_63..32)
   endif
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

00011

010

00000

sel

Format:

MTGC0 rt, rd, sel

MIPS32

Move to Guest Coprocessor 0

Purpose:

Move to Guest Coprocessor 0

To move the contents of a general register to a guest coprocessor 0 register.

Description:

 Guest.CPR[0, rd, sel] = GPR[rt]

The contents of general register rt are loaded into the guest context coprocessor 0 register speciied by the combination of rd and sel. Not all guest context coprocessor 0 registers support the sel ield. In those instances, the sel ield must be set to zero.

When the guest context coprocessor 0 destination register speciied is the EntryLo0 or the EntryLo1 register, bits

31:30 appear as the RI/XI ields of the destination register. This feature supports 32-bit addressing mode compatibility on a MIPS64 system.

Restrictions:

The results are UNDEFINED if guest context coprocessor 0 does not contain the register as speciied by rd and sel or the destination register is the Guest.Count register, which is read-only

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

MTGC0 must behave exactly the same as the corresponding guest MTC0instruction, exceptthatit will not cause exceptions that are speciic to guest, such as GPSI and GSFC. Speciically, if the guest register is replicated in guest context, then the write must complete, if the register is Reserved for Architecture/Implementation or is Not Available, the write is ignored, if the register is Shared (such as WatchHi) then the write always completes but does not effect ields invisible to guest.

In a 64-bit processor, the MTGC0 instruction writes all 64 bits of register rt into the guest context coprocessor register speciied by rd and sel if that register is a 64-bit register.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3_VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   data = GPR[rt]
   reg = rd
   if (reg,sel = EntryLo1 or reg,sel = EntryLo0) then
      Guest.CPR[0,reg,sel]_29..0= data_29..0
      Guest.CPR[0,reg,sel]₆₃= data₃₁
      Guest.CPR[0,reg,sel]₆₂= data₃₀
      Guest.CPR[0,reg,sel]_61:30= 0³²
   else if (Width(CPR[0,reg,sel]) = 64) then
      Guest.CPR[0,reg,sel] = data
   else
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

00011

110

00000

sel

Format:

MTHGC0 rt, rd, sel

MIPS32 Release 5

Move to High Guest Coprocessor 0

Purpose:

Move to High Guest Coprocessor 0

To move the contents of a general register to the upper 32-bits of a guest coprocessor 0 register that has been extended by 32-bits.

Description:

 Guest.CPR[0, rd, sel][63:32] = GPR[rt]

The contents of general register rt are loaded into the guest coprocessor 0 register speciied by the combination of rd and sel. Not all coprocessor 0 registers support the the sel ield. In those instances, the sel ield must be set to zero.

When the guest coprocessor 0 destination register speciied is the EntryLo0 or the EntryLo1 register, bits 1:0 of the

GPR appear at bits 31:30 of EntryLo0 or the EntryLo1 ields. This is to compensate for RI/XI which were shifted to bits 63:62 by MTC0 of EntryLo0 or the EntryLo1.

If RI/XI are not supported,then the shift must still occur, but

MFHC0 willreturn 0s forthese two ields. The GPR is right shifted by 2 to vacate the lower 2-bits, and 2 0s are is written to the upper 32-bits MIPS64 EntryLo0 or EntryLo1, excluding RI/XI shifted in from the left. The result that were placed in bits 63:62 i.e., the write must appear atomic as if both MTC0 and MTHC0 occured together.

This feature supports MIPS32 backward compatability on a MIPS64 system.

Restrictions:

The results are UNDEFINED if guest coprocessor 0 does not contain a register as speciied by rd and sel, or if the register exists but is not extended by 32-bits, or the register is extended for XPA, but XPA is not enabled. XPA is a

Release 5 feature.

MTHGC0 must behave exactly the same as the corresponding guest MTHC0instruction, exceptthatit will not cause exceptions that are speciic to guest, such as GPSI and GSFC. Speciically, if the guest register is replicated in guest context, then the write must complete, if the register is Reserved for Architecture/Implementation or is Not Available, the write is ignored, if the register is Shared (such as WatchHi) then the write always completes but does not effect ields invisible to guest.

In a 64-bit processor, the MTHC0 instruction writes only the lower 32 bits of register rt into the upper 32-bits of the guest coprocessor register speciied by rd and sel if that register is extended by MIPS32 Release 5. Speciically, the only registers extended by MIPS32 Release 5 are those required for the feature XPA, and those registers are identical to the same registers in the MIPS64 architecture, other than EntryLo0 or the EntryLo1.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Operation:

if IsCoprocessorEnabled(0) then
   data = GPR[rt]
   reg = rd
   if (reg,sel = EntryLo1 or reg,sel = EntryLo0) then
      if (Root.Config3_LPA = 1 and Root.PageGrain_ELPA = 1) then // PABITS > 36
         Guest.CPR[0,reg,sel]_31..30= data_1..0
         Guest.CPR[0,reg,sel]_61:32= data_31..2 and ((1<<(PABITS-36))-1)
         Guest.CPR[0,reg,sel]_61:32= 0²
      endif
   else
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBGINV

001011

Format:

TLBGINV

MIPS32

Guest TLB Invalidate

Purpose:

Guest TLB Invalidate

Index match. The virtual address isTLBGINV invalidates a set of guest TLB entries based on ASID and guest ignored in the match.

Implementation of the TLBGINV instruction is optional. The implementation of this instruction is indicated by the IE ﬁeld in Conﬁg4.

Implementation of EntryHI_EHINV ﬁeld is required for implementation of TLBGINV instruction.

Support for TLBGINV is recommended for implementations supporting VTLB/FTLB type TLB’s.

Description:

On execution ofthe TLBGINV instruction,the set of guest TLB entries with matching ASID are marked invalid, excluding those guest TLB entries which have their G bit set to 1.

The EntryHI_ASID ﬁeld has to be set to the appropriate ASID value before executing the TLBGINV instruction.

Behavior of the TLBGINV instruction applies to all applicable guest TLB entries and is unaffected by the setting of the Guest.Wired register.

For JTLB-based MMU(Conﬁg_MT=1):

All matching entries in the guest JTLB are invalidated. Index is unused.

For VTLB/FTLB -based MMU(Conﬁg_MT=4):

A TLBGINV with Index set in guest VTLB range causes all matching entries in the guest VTLB to be invalidated. A TLBGINV with Index set in guest FTLB range causes all matching entries in the single addressed guest

FTLB set to be invalidated.

If TLB invalidate walk is implemented in software (Conﬁg4_IE=2), then software must do these steps:

1.one TLBGINV instruction is executed with an index in guest VTLB range (invalidates all matching guest

VTLB entries)

2.a TLBGINV instruction is executed for each guest FTLB set (invalidates all matching entries in guest FTLB set)

If TLB invalidate walk is implemented in hardware (Conﬁg4_IE=3), then software must do these steps:

1.one TLBGINV instruction is executed (invalidates all matching entries in both guest FTLB & guest VTLB).

In this case, Index is unused.

In an implementation supporting GuestID (GuestCtl0_G1=1), matching of guest TLB entries includes comparison of the TLB entry GuestID with the Root GuestID control ﬁeld, GuestCtl1RID .

Note that the TLBGINV instruction only invalidates guest virtual address translations in the guest TLB, invalidation of guest physical address translations requires execution of the equivalent TLBINV instruction sequence in the root

TLB.

The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of available TLB entries (for the case of ConﬁgMT=4).

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

For processors that do not include a TLB, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

   if (Guest.Config_MT=1 or
      (Guest.Config_MT=4 & Guest.Cοnfig4_IE=2 & Index≤ Guest.Config1_{MMU_SIZE-1}))
      startnum = 0
      endnum = Guest.Config1_{MMU_SIZE-1}
   endif
   // treating VTLB and FTLB as one array
   if (Guest.Config_MT=4 & Guest.Cοnfig4_IE=2 & Index > Guest.Config1_{MMU_SIZE-1})
      startnum = start of selected Guest FTLB set // implementation specific
      endnum = end of selected Guest FTLB set - 1 //implementation specifc
   endif
   if (Guest.Config_MT=4 & Guest.Cοnfig4_IE=3))
      startnum = 0
      endnum = Guest.Config1_{MMU_SIZE-1}+
      ((Guest.Config4_FTLBWays + 2) * Guest.Config4_FTLBSets)
   endif
   if IsCoprocessorEnabled(0) then
      for (i = startnum to endnum)
         if ((Guest.TLB[i]_ASID = Guest.EntryHi_ASID) & (Guest.TLB[i]_G = 0))
             if (GuestCtl0_G1= 1)
                if (Guest.TLB[i]_GuestID = GuestCtl1_RID)
                   Guest.TLB[i]_{hardware_invalid}= 1
                endif
             else
                   Guest.TLB[i]_{hardware_invalid}= 1
             endif
         endif
      endfor
   else
      SignalException(CoprocessorUnusable, 0)
   endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBGINVF

001100

Format:

TLBGINVF

MIPS32

Guest TLB Invalidate Flush

Purpose:

Guest TLB Invalidate Flush

TLBGINVF invalidates a set of Guest TLB entries based on Index match. The virtual address and ASID are ignored in the match.

Implementation of the TLBGINVF instruction is optional. The implementation of this instruction is indicated by the

IE ield in Conig4. the EntryHIEHINV ield is required for

Implementation ofimplementation of TLBGINV and TLBGINVF instructions.

Support for TLBGINVF is recommend for implementations supporting VTLB/FTLB type TLB's.

Description:

On execution of the TLBGINVF instruction, all entries within range of guest Index are invalidated.

Behavior of the TLBGINVF instruction applies to all applicable guest TLB entries and is unaffected by the setting of the Wired register.

For JTLB-based MMU(Conig_MT=1):

TLBGINVF causes all entries in the guest JTLB to be invalidated. Index is unused.

For VTLB/FTLB-based MMU(Conig_MT=4):

TLBINVF with Index in guest VTLB range causes all entries in the guest VTLB to be invalidated.

TLBINVF with Index in guest FTLB range causes all entries in the single corresponding set in the guest FTLB to be invalidated.

If TLB invalidate walk is implemented in software (Conig4_IE=2), then software must do these steps:

1.one TLBGINV instruction is executed with an index in guest VTLB range (invalidates all matching guest

VTLB entries)

2.a TLBGINV instruction is executed for each guest FTLB set (invalidates all matching entries in guest FTLB set)

If TLB invalidate walk is implemented in hardware (Conig4_IE=3), then software must do these steps:

1.one TLBGINV instruction is executed (invalidates all matching entries in both guest FTLB & guest VTLB).

In this case, Index is unused.

In an implementation supporting GuestID (GuestCtl0_G1=1), matching of guest TLB entries includes comparison of the TLB entry GuestID with the Root GuestID control ield, GuestCtl1RID .

Note that the TLBGINVF instruction only invalidates guest virtual address translations in the guest TLB, invalidation of guest physical address translations requires execution of the equivalent TLBINVF instruction sequence in the root

TLB.

Restrictions:

The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries visible as deined by the Conig4 register.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

For processors that do notinclude the standard TLB MMU, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

   if ( Guest.Config_MT=1 or
      (Guest.Config_MT=4 & Guest.Config4_IE=2 & Index<= Guest.Config1_{MMU_SIZE-1}))
      startnum = 0
      endnum = Guest.Config1_{MMU_SIZE-1}
   endif
   // treating VTLB and FTLB as one array
   if (Guest.Config_MT=4 & Guest.Config4_IE=2 & Index > Guest.Config1_{MMU_SIZE-1})
      startnum = start of selected Guest FTLB set // implementation specific
      endnum = end of selected Guest FTLB set - 1 //implementation specifc
   endif
   if (Guest.Config_MT=4 & Guest.Config4_IE=3))
      startnum = 0
      endnum = Guest.Config1_{MMU_SIZE-1}+
      ((Guest.Config4_FTLBWays + 2) * Guest.Config4_FTLBSets)
   endif
   if IsCoprocessorEnabled(0) then
      for (i = startnum to endnum)
         if (GuestCtl0_G1= 1)
             if (Guest.TLB[i]_GuestID = GuestCtl1_RID)
                Guest.TLB[i]_{hardware_invalid}= 1
             endif
         else
                Guest.TLB[i]_{hardware_invalid}= 1
         endif
      endfor
   else
      SignalException(CoprocessorUnusable, 0)
   endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBGP

010000

Format:

TLBGP

MIPS32

Probe Guest TLB for Matching Entry

Purpose:

Probe Guest TLB for Matching Entry

To ind a matching entry in the Guest TLB, initiated from root mode.

Description:

The Guest.Index register is loaded with the address of the Guest TLB entry whose contents match the contents of the

Guest.EntryHi register. If no Guest TLB entry matches, the high-order bit of the Guest.Index register is set.

In an implementation supporting GuestID (GuestCtl0_G1=1), if the GuestID read does not match GuestCtl1_RID, then the match fails.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

If an implementation detects multiple matches, and does not detect all multiple matches on TLB write, then a TLBGP instruction can take a Machine Check Exception if multiple matches occur.

For processors that do not include a TLB in the guest context, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3_VZ = 0) then
       SignalException(ReservedInstruction, 0)
       break
   endif
   Guest.Index = 1 || UNPREDICTABLE³¹
// If a set-associative TLB is used, then a single set may be probed.
for i in 0...Guest.TLBEntries-1
      if (((Guest.TLB[i]_VPN2 and ~(Guest.TLB[i]_Mask)) =
             (Guest.EntryHi_VPN2 and ~(Guest.TLB[i]_Mask))) and
             (Guest.TLB[i]_R = Guest.EntryHi_R) and
             ((Config4_IE>= 2)and not TLB[i]_{hardware_invalid}) and
             (Guest.TLB[i]_G or (Guest.TLB[i]_ASID = Guest.EntryHi_ASID))) then
                   if (GuestCtl0_G1= 1)
                          if (Guest.TLB[i]_GuestID = GuestCtl1_RID)
                                 Guest.Index = i
                          endif
                   else
                       Guest.Index = i
                endif
         endif
   endfor
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Machine Check (implementation dependent)

Reserved Instruction

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBGR

001001

Format:

TLBGR

MIPS32

Read Indexed Guest TLB Entry

Purpose:

Read Indexed Guest TLB Entry

To read an entry from the Guest TLB into the guest context, initiated from root mode.

Description:

The Guest.EntryHi, Guest.EntryLo0, Guest.EntryLo1, and Guest.PageMask registers are loaded with the conthe Guest.Index tents of the Guest TLB entry pointed to by register. Note that the value written to the

Guest.EntryHi, Guest.EntryLo0, and Guest.EntryLo1 registers may be different from that originally written to the

TLB via these registers in that:

The value returned in the VPN2 ield of the EntryHi register may have those bits set to zero corresponding to the

one bits in the Mask ield of the TLB entry (the least signiicant bit of VPN2 corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.

The value returned in the PFN ield of the EntryLo0 and EntryLo1 registers may have those bits set to zero cor-

responding to the one bits in the Mask ield of the TLB entry (the least signiicant bit of PFN corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed after a TLB entry is written and then read.

The value returned in the G bit in both the EntryLo0 and EntryLo1 registers comes from the single G bit in the

TLB entry. Recall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLo1 when the TLB was written. the GuestCtl1RID ield is written

In an implementation supporting GuestID,if the TLB entry is not marked invalid, with the GuestID of the TLB entry read.

Restrictions:

The operation is UNDEFINED if the contents of the Guest.Index register are greater than or equal to the number of

TLB entries in the guest context.

If root-mode access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

For processors that do not include a TLB in the guest context, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3_VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   i = Guest.Index
   if i > (Guest.TLBEntries - 1) then
      UNDEFINED
   endif
   if (Config4_IE >= 2 && Guest.TLB[i]_EHINV = 1) then
      GuestCtl1_RID= 0
      Guest.Pagemask_Mask= 0
      Guest.EntryHi = 0
      Guest.EntryLo1 = 0
      Guest.EntryLo0 = 0
      Guest.EntryHi_EHINV= 1
      break
   endif
   if (GuestCtl0_G1= 1)
      GuestCtl1_RID= Guest.TLB[i]_GuestID
   endif
   Guest.PageMask_Mask= Guest.TLB[i]_Mask
   Guest.EntryHi = Guest.TLB[i]_R || 0^Fill ||
         (Guest.TLB[i]_VPN2 and not Guest.TLB[i]_Mask) || # Masking impl dependent
         0⁵ || Guest.TLB[i]_ASID
   Guest.EntryLo1 = 0^Fill ||
         (Guest.TLB[i]_PFN1 and not Guest.TLB[i]_Mask) || # Masking impl dependent
         Guest.TLB[i]_C1 || Guest.TLB[i]_D1 || Guest.TLB[i]_V1 || Guest.TLB[i]_G
   Guest.EntryLo0 = 0^Fill ||
         (Guest.TLB[i]_PFN0 and not Guest.TLB[i]_Mask) || # Masking impl dependent
         Guest.TLB[i]_C0 || Guest.TLB[i]_D0 || Guest.TLB[i]_V0 || Guest.TLB[i]_G
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBGWI

001010

Format:

TLBGWI

MIPS32

Write Indexed Guest TLB Entry

Purpose:

Write Indexed Guest TLB Entry

To write a Guest TLB entry indexed by the Index register, initiated from root mode.

Description:

The Guest TLB entry pointed to by the Guest.Index registerthe Guest.EntryHi, is written from the contents of

Guest.EntryLo0, Guest.EntryLo1, and Guest.PageMask registers. The information written to the Guest TLB

entry may be different from that in the Guest.EntryHi, Guest.EntryLo0, and Guest.EntryLo1 registers, in that:

The value written to the VPN2 ield of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of the PageMask register (the least signiicant bit of VPN2 corresponds to the least significant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

The value written to the PFN0 and PFN1 ields of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of PageMask register (the least signiicant bit of PFN corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLo0 and EntryLo1 regis-

ters.

In an implementation supporting GuestID, GuestCtl1_RID is written in the TLB entry.

If EHINV is implemented, the TLBGWI instruction also acts as an explicit TLB entry invalidate operation. The Guest

TLB entry pointed to by the Guest.Index register is marked invalid when guest EntryHI_EHINV=1.

When EntryHI_EHINV=1, no machine check generating error conditions exist.

Implementation of the TLBGWI invalidate feature is required if the TLBGINV and TLBGINVF instructions are implemented, optional otherwise.

Restrictions:

The operation is UNDEFINED if the contents of the Guest.Index register are greater than or equal to the number of

TLB entries in the guest context.

If access to the root Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

On an FTLB enabled system, if Guest.Index is in FTLB range and the page size speciied does not match FTLB page size, recommended behavior is that the write not complete and a Machine Check Exception be signaled.

On an FTLB enabled system, for a write in FTLB range, if the VPN is inconsistent with Index, it is recommended that a Machine Check Exception be signaled.

Itisimplementation dependent whether multiple TLB matches are detected on a TLBGWI,though itisrecommended. If a TLB write detects multiple matches, but not necessarily all multiple matches, then it is recommended that a TLB lookup or TLB probe operation signal a Machine Check Exception on detection of multiple matches.

If multiple match detection is implemented,then on detection,itis recommended thatthe multiple match be invalidated and the write completed. It is recommended that no Machine Check Exception be signaled.

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction Exception, taken in guest mode.

For processors that do not include a TLB in the guest context, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3_VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   i = Guest.Index
   if (Config4_IE>= 2) then
      Guest.TLB[i]_{hardware_invalid}= 0
      if ( EntryHI_EHINV=1 ) then
         Guest.TLB[i]_{hardware_invalid}= 1
      endif
   endif
   Guest.TLB[i]_Mask= Guest.PageMask_Mask
   Guest.TLB[i]_{R =}Guest.EntryHi_R
   Guest.TLB[i]_VPN2= Guest.EntryHi_VPN2and not Guest.PageMask_Mask # Impl dependent
   Guest.TLB[i]_ASID= Guest.EntryHi_ASID
   Guest.TLB[i]_G= Guest.EntryLo1_G and Guest.EntryLo0_G
   Guest.TLB[i]_PFN1= Guest.EntryLo1_PFNand not Guest.PageMask_Mask # Impl dependent
   Guest.TLB[i]_C1= Guest.EntryLo1_C
   Guest.TLB[i]_D1= Guest.EntryLo1_D
   Guest.TLB[i]_V1= Guest.EntryLo1_V
   Guest.TLB[i]_PFN0= Guest.EntryLo0_PFNand not Guest.PageMask_Mask # Impl dependent
   Guest.TLB[i]_C0= Guest.EntryLo0_C
   Guest.TLB[i]_D0= Guest.EntryLo0_D
   Guest.TLB[i]_V0= Guest.EntryLo0_V
   if (GuestCtl0_G1) then
      Guest.TLB[i]_GuestID= GuestCtl1_RID
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Machine Check (disabled if guest EntryHI_EHINV=1.)

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBWR

001110

Format:

TLBGWR

MIPS32

Write Random Guest TLB Entry

Purpose:

Write Random Guest TLB Entry

To write a Guest TLB entry indexed by the Random register, initiated from root mode.

Description:

The Guest TLB entry pointed to by the Guest.Random register is written from the contents of the Guest.EntryHi,

Guest.EntryLo0, Guest.EntryLo1, and Guest.PageMask registers.

The information written to the Guest TLB entry may be different from that in the Guest.EntryHi, Guest.EntryLo0, and Guest.EntryLo1 registers, in that:

The value written to the VPN2 ield of the Guest TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of the Guest.PageMask register (the least signiicant bit of VPN2 corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a Guest TLB write.

The value written to the PFN0 and PFN1 ields of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of Guest.PageMask register (the least signiicant bit of PFN corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a Guest TLB write.

The single G bit in the Guest TLB entry is set from the logical AND of the G bits in the Guest.EntryLo0 and

Guest.EntryLo1 registers.

In an implementation supporting GuestID, GuestCtl1_RID is written in the TLB entry.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

On an VTLB/FTLB enabled implementation, if the Pagemask register contains a page size differing from the FTLB page size deined in Conig4, then the write goes into a random entry in the VTLB.

Itis implementation dependent whether multiple TLB matches are detected on a TLBGWR,though itis recommended. If a TLB write detects multiple matches, but not necessarily all multiple matches, then a TLB lookup or TLB probe operation should signal a Machine Check Exception on detection of multiple matches.

If multiple match detection is implemented, then on detection, the multiple match should be invalidated and the write completed. No Machine Check Exception should be signaled.

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

For processors that do not include a TLB in the guest context, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   i = Guest.Random
   if (Config4_IE >= 2) then
      Guest.TLB[i]_{hardware_invalid}= 0
      if ( EntryHI_EHINV=1 ) then
         Guest.TLB[i]_{hardware_invalid}= 1
      endif
   endif
   Guest.TLB[i]_Mask= Guest.PageMask_Mask
   Guest.TLB[i]_{R =}Guest.EntryHi_R
   Guest.TLB[i]_VPN2= Guest.EntryHi_VPN2and not Guest.PageMask_Mask # Impl. dependent
   Guest.TLB[i]_ASID= Guest.EntryHi_ASID
   Guest.TLB[i]_G= Guest.EntryLo1_G and Guest.EntryLo0_G
   Guest.TLB[i]_PFN1= Guest.EntryLo1_PFNand not PageMask_Mask # Impl. dependent
   Guest.TLB[i]_C1= Guest.EntryLo1_C
   Guest.TLB[i]_D1= Guest.EntryLo1_D
   Guest.TLB[i]_V1= Guest.EntryLo1_V
   Guest.TLB[i]_PFN0= Guest.EntryLo0_PFNand not PageMask_Mask # Impl. dependent
   Guest.TLB[i]_C0= Guest.EntryLo0_C
   Guest.TLB[i]_D0= Guest.EntryLo0_D
   Guest.TLB[i]_V0= Guest.EntryLo0_V
   if (GuestCtl0_G1) then
      Guest.TLB[i]_GuestID= GuestCtl1_RID
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Machine Check (implementation dependent)

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBINV

000011

Format:

TLBINV

MIPS32

TLB Invalidate

Purpose:

TLB Invalidate

Description:

The TLBINV instruction is unmodiied from the base architectural deinition, except in an implementation supporting

GuestID:

When executing in Guest mode, if the GuestID read does not match GuestCtl1_ID, then the TLB entry is not

modiied.

When executing in Root mode, if the GuestID read does not match GuestCtl1_RID, then the TLB entry is not

modiied. Note that this only applies to the root TLB, invalidation of guest virtual address translations requires execution of the equivalent TLBGINV instruction sequence to modify the guest TLB.

Restrictions:

Unchanged from the base architecture.

Exceptions:

Unchanged from the base architecture.

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBINVF

000100

Format:

TLBINVF

MIPS32

TLB Invalidate Flush

Purpose:

TLB Invalidate Flush

Description:

The TLBINVF instruction is unmodiied from the base architectural deinition, except in an implementation supporting GuestID:

When executing in Guest mode, if the GuestID read does not match GuestCtl1_ID, then the TLB entry is not

modiied.

When executing in Root mode, if the GuestID read does not match GuestCtl1_RID, then the TLB entry is not

modiied. Note that this only applies to the root TLB, invalidation of guest virtual address translations requires execution of the equivalent TLBGINVF instruction sequence to modify the guest TLB.

Restrictions:

Unchanged from the base architecture.

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBP

001000

Format:

TLBP

MIPS32

Probe TLB for Matching Entry

Purpose:

Probe TLB for Matching Entry

To ind a matching entry in the TLB.

Description:

The TLBP instruction is unmodiied from the base architectural deinition, exceptin an implementation supporting

GuestID:

When executing in Guest mode, if the GuestID read does not match GuestCtl1_ID, then the match fails.

When executing in Root mode, if the GuestID read does not match GuestCtl1_RID, then the match fails.

Restrictions:

Unchanged from the base architecture.

Operation:

if IsCoprocessorEnabled(0) then
Index = 1 || UNPREDICTABLE³¹
for i in 0...TLBEntries-1
if ((TLB[i]_VPN2 & ~(TLB[i]_Mask)) = (EntryHi_VPN2 & ~(TLB[i]_Mask))) and
(TLB[i]_R = EntryHi_R) and
(Config4_IE >= 2 && TLB[i]_{hardware_invalid} != 1) and
((IsRootMode() and (TLB[i]_GuestID = GuestCtl1_RID)) or
(IsGuestMode() and (TLB[i]_GuestID = GuestCtl1_ID))) and
((TLB[i]_G = 1) or (TLB[i]_ASID = EntryHi_ASID)) then
Index = i
endif
endfor
else
SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Machine Check (implementation deined)

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBR

000001

Format:

TLBR

MIPS32

Read Indexed TLB Entry

Purpose:

Read Indexed TLB Entry

To read an entry from the TLB.

Description:

The TLBR instruction is unmodiied from the base architectural deinition, exceptin an implementation supporting

GuestID:

When executing in Guest mode, if the GuestID read does not match GuestCtl1_ID, then the TLB related CP0 reg-

isters are zeroed and EHINV is set to 1.

When executing in Root mode and the TLB entry is not marked as invalid, GuestCtl1_RIDis set to the GuestID of

the TLB entry read, else it is set to 0.

Restrictions:

The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries in the processor.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

For processors that do notinclude the standard TLB MMU, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
   i = Index
   if i > (TLBEntries - 1) then
      UNDEFINED
   endif
   if (Config4_IE>= 2 && TLB[i]_{hardware_invalid}=1) then
      if GuestCtl0_G1=1
         if (GuestCtl0_GM=0 or (GuestCtl0_GM=1 and (Root.Debug_DM=1 or
             Root.Status_ERL=1 or Root.Status_EXL=1))) then
                GuestCtl1_RID= 0 // RID only updated in root mode
         endif
      endif
      // Remaining state is handled similarly in root and guest modes.
      Pagemask_Mask= 0
      EntryHi = 0
      EntryLo1 = 0
      EntryLo0 = 0
      EntryHi_EHINV= 1
      break
   endif
   PageMask_Mask= TLB[i]_Mask
   EntryHi = TLB[i]_R || 0^Fill ||
             (TLB[i]_VPN2 and not TLB[i]_Mask) || # Masking implementation dependent
   EntryLo1 = 0^Fill ||
             (TLB[i]_PFN1 and not TLB[i]_Mask) || # Masking mplementation dependent
             TLB[i]_C1 || TLB[i]_D1 || TLB[i]_V1 || TLB[i]_G
   EntryLo0 = 0^Fill ||
             (TLB[i]_PFN0 and not TLB[i]_Mask) || # Masking mplementation dependent
             TLB[i]_C0 || TLB[i]_D0 || TLB[i]_V0 || TLB[i]_G
   # if in guest mode, if the TLB entry guest id != guest id then zero the result
   if (GuestCtl0_G1= 1)
      if (GuestCtl0_GM=1) and (Root.Debug_DM=0) and
         (Root.Status_ERL=0) and (Root.Status_EXL=0) then
             if (TLB[i]_ID != GuestCtl1_ID) then
                Pagemask_Mask= 0
                EntryHi = 0
                EntryLo1 = 0
                EntryLo0 = 0
                EntryHi_EHINV= 1
             endif
      else #in root mode, RID with GuestID
         GuestCtl1_RID= TLB[i]_GuestID
      endif
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBWI

000010

Format:

TLBWI

MIPS32

Write Indexed TLB Entry

Purpose:

Write Indexed TLB Entry

To write a TLB entry indexed by the Index register.

Description:

The TLBWI instruction is unmodiied from the base architecture, except in an implementation supporting GuestID:

When executing in Guest mode, GuestCtl1_ID is written in the guest TLB entry.

When executing in Root mode GuestCtl1_RID is written in the root TLB entry.
It is expected that a Guest entry in the Root TLB must have its Global(G) bit set to 1 on a TLB write. This is because the ASID ield is not applicable for a Guest entry in the Root TLB.

If EHINV is implemented, the TLBWI instruction also acts as an explicit TLB entry invalidate operation. The TLB entry pointed to by the Index register is marked invalid when EntryHIEHINV=1.

When EntryHI_EHINV=1, no machine check generating error conditions exist.

Restrictions:

Unmodiied from the base architecture.

Operation:

if IsCoprocessorEnabled(0) then
   i = Index
   if ( Config4_IE>= 2) then
      TLB[i]_{hardware_invalid}= 0
      if (EntryHI_EHINV=1) then
         TLB[i]_{hardware_invalid}= 1
      endif
   endif
   TLB[i]_Mask= PageMask_Mask
   TLB[i]_{R =}EntryHi_R
   TLB[i]_VPN2= EntryHi_VPN2and not PageMask_Mask # Implementation dependent
   TLB[i]_ASID= EntryHi_ASID
   if (GuestCtl0_G1) then
         if ((GuestCtl0_RAD=0) and IsRootMode() and (GuestCtl1_RID != 0))
             TLB[i]_G= 1
         else
             TLB[i]_G= EntryLo1_G and EntryLo0_G
         endif
   else
         TLB[i]_G= EntryLo1_G and EntryLo0_G
   endif
   if ( IsRootMode() ) then
      TLB[i]_GuestID= GuestCtl1_RID
      TLB[i]_GuestID= GuestCtl1_ID
   endif
   TLB[i]_PFN1= EntryLo1_PFNand not PageMask_Mask # Implementation dependent
   TLB[i]_C1= EntryLo1_C
   TLB[i]_D1= EntryLo1_D
   TLB[i]_V1= EntryLo1_V
   TLB[i]_PFN0= EntryLo0_PFNand not PageMask_Mask # Implementation dependent
   TLB[i]_C0= EntryLo0_C
   TLB[i]_D0= EntryLo0_D
   TLB[i]_V0= EntryLo0_V
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Unmodiied from the base architecture.

Encoding:

COP0

010000

000 0000 0000 0000 0000

TLBWR

000110

Format:

TLBWR

MIPS32

Write Random TLB Entry

Purpose:

Write Random TLB Entry

To write a TLB entry indexed by the Random register.

Description:

The TLB entry pointed to by the Random register is written from the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers.

The information written to the TLB entry may be different from that in the EntryHi, EntryLo0, and EntryLo1 registers, in that:

The value written to the VPN2 ield of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of the PageMask register (the least signiicant bit of VPN2 corresponds to the least significant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

The value written to the PFN0 and PFN1 ields of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of PageMask register (the least signiicant bit of PFN corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLo0 and EntryLo1 reg-

isters.

In an implementation supporting GuestID, GuestCtl1_RID is written in the TLB entry.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

On an VTLB/FTLB enabled implementation, if the Pagemask register contains a page size differing from the FTLB page size deined in Conig4, then the write goes into a random entry in the VTLB.

It is implementation dependent whether multiple TLB matches are detected on a TLBWR, though it is recommended.

If a TLB write detects multiple matches, but not necessarily all multiple matches,then a TLB lookup or TLB probe operation should signal a Machine Check Exception on detection of multiple matches.

If multiple match detection is implemented, then on detection, the multiple match should be invalidated and the write completed. No Machine Check Exception should be signaled.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3_VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   if (Config4_IE = 1) then
      TLB[i]_{hardware_invalid}= 0
      if ( EntryHI_EHINV=1 ) then
         TLB[i]_{hardware_invalid}= 1
      endif
   endif
   TLB[i]_Mask= PageMask_Mask
   TLB[i]_{R =}EntryHi_R
   TLB[i]_VPN2= EntryHi_VPN2and not PageMask_Mask # Impl. dependent
   TLB[i]_ASID= EntryHi_ASID
   if (GuestCtl0_G1) then
      if ((GuestCtl0_RAD=0) and IsRootMode() and (GuestCtl1_RID != 0))
         TLB[i]_G= 1
      else
         TLB[i]_G= EntryLo1_G and EntryLo0_G
      endif
   else
      TLB[i]_G= EntryLo1_G and EntryLo0_G
   endif
   TLB[i]_PFN1= EntryLo1_PFNand not PageMask_Mask # Impl. dependent
   TLB[i]_C1= EntryLo1_C
   TLB[i]_D1= EntryLo1_D
   TLB[i]_V1= EntryLo1_V
   TLB[i]_PFN0= EntryLo0_PFNand not PageMask_Mask # Impl. dependent
   TLB[i]_C0= EntryLo0_C
   TLB[i]_D0= EntryLo0_D
   TLB[i]_V0= EntryLo0_V
   if (GuestCtl0_G1) then
      TLB[i]_GuestID= GuestCtl1_RID
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Machine Check (implementation dependent)