Encoding:

Format:

LWXS rd, index(base)

Purpose:

Load Word Indexed, Scaled

To load a word from memory as a signed value, using scaled indexed addressing.

Description:

GPR[rd] = memory[GPR[base] + (GPR[index] × 4)]

The contents of GPR index is multiplied by 4 and the result is added to the contents of GPR base to form an effective address. The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched, sign-extended to the GPR register length if necessary, and placed in GPR rd.

Restrictions:

The effective address must be naturally-aligned. If either of the 2 least-significant bits of the address is non-zero, an

Address Error exception occurs.

Operation:

vAddr = (GPR[index]29..0 || 02) + GPR[base]
if vAddr1..0 != 02 then
   SignalException(AddressError)
endif
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
memword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
GPR[rd] = memword

Exceptions:

TLB Refill, TLB Invalid, Bus Error, Address Error

Encoding:

Format:

MADDP rs, rt

Purpose:

Multiply and Add Polynomial Basis Word to Hi,Lo

To multiply two 32-bit binary polynomial values and polynomial-basis add the result to Hi, Lo.

Description:

(LO,HI,ACX) = PolyMult(GPR[rs], GPR[rt]) xor (LO,HI,ACX)

The 32-bit word value in GPR rs is polynomial-basis multiplied by the 32-bit value in GPR rt, treating both operands as binary polynomial values, to produce a 64-bit result. The product is polynomial-basis added (XORed) to the 64-bit concatenated value of HI and LO, and the zero-extended result is written back into HI and LO. Although MADDP is formally deined to operate on special register ACX as well, its value can never be changed by the operation, nor can its input value affect the result. No arithmetic exception occurs under any circumstances.

Restrictions:

This instruction does not provide the capability of writing directly to a target GPR.

Operation:

temp = (HI31..0 || LO31..0) xor PolyMult(GPR[rs]31..0,GPR[rt]31..0)
HI = sign_extend(temp63..32)
LO = sign_extend(temp31..0)
ACX = ACX

Exceptions:

None

Encoding:

Format:

MADDU rs, rt

Purpose:

Multiply and Add Unsigned Word to Hi,Lo

To multiply two unsigned words and add the result to ACX, HI, LO.

Description:

(LO,HI,ACX) = (GPR[rs]  * GPR[rt]) + (LO,HI,ACX)

The 32-bit word value in GPR rs is multiplied by the 32-bit value in GPR rt, treating both operands as unsigned values, to produce a 64-bit result. The product is added to the 72-or-more-bit concatenated value of ACX, HI, and LO, and the carry-extended result is written back into ACX, HI, and LO. No arithmetic exception occurs under any circumstances.

Restrictions:

This instruction does not provide the capability of writing directly to a target GPR.

Operation:

temp = (ACXACXMSB..0 || HI31..0|| LO31..0) + (GPR[rs]31..0* GPR[rt]31..0)
ACX = zero_extend(tempACXMSB+64..64)
HI = sign_extend(temp63..32)
LO = sign_extend(temp31..0)

Exceptions:

None

Encoding:

Format:

MFLHXU rd

Purpose:

Move from Extended Carry, Hi and Lo (Unsigned)

Extract extended Hi/Lo state.

Description:

 GPR[rd] = LO; LO = HI; HI = ACX; ACX = 0;

The value in special register LO is written to GPR rd. The value in special register HI is then written to special register

LO, the extended accumulator bits ACX are zero-extended and copied to HI, and the extended accumulator bits ACX

are cleared

• The number of ACX extended accumulator bits is implementation dependent, ranging from 8 to 64 bits.

• If 64-bit operations are not available and enabled, at most the least-signiicant 32 bits of ACX will be copied to

HI, but the whole ACX ield will then be cleared.

Restrictions:

None

Operation:

newHI = zero_extend(ACX)
newLO = HI
GPR[rd] = LO
LO = newLO
HI = newHI
ACX = 0

Exceptions:

None

Encoding:

Format:

MTLHX rs

Purpose:

Move to Lo, Hi, and Extended Carry

Set extended Hi/Lo state.

Description:

ACX = HI; HI = LO; LO = GPR[rs] ;

The value special register HI is written to the extended accumulator bits ACX. The value in special register LO is then written to special register HI, and the value in GPR rs is written to special register LO. This is the reverse of the operation of the MFLHXU instruction.

• The number of ACX extended accumulator bits is implementation-dependent, ranging from 8 to 64 bits. If the HI register contains more signiicant bits than the number of implemented ACX bits, that information is discarded without raising an exception.

• If 64-bit operations are not enabled, at most the least-signiicant 32 bits of HI will be copied to ACX.

Restrictions:

None

Operation:

newLO = GPR[rs]
newHI = LO
ACX = HIACXMSB..0
HI = newHI
LO = newLO

Exceptions:

None

Encoding:

Format:

MULTP rs, rt

Purpose:

Multiply Binary Polynomial Basis Word

To multiply two 32-bit binary polynomial values

Description:

(LO, HI) = BinPolyMult(GPR[rs], GPR[rt])

The 32-bit word value in GPR rt is polynomial-basis multiplied by the 32-bit value in GPR rs, treating both operands as binary polynomial values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the high-order 32-bit word is placed into special register HI. The special register ACX is cleared.

No arithmetic exception occurs under any circumstances.

Restrictions:

None

Operation:

prod = PolyMult(GPR[rs]31..0, GPR[rt]31..0)
LO = sign_extend(prod31..0)
HI = sign_extend(prod63..32)
ACX = 0

Exceptions:

None

Encoding:

Format:

MULTU rs, rt

Purpose:

Multiply Unsigned Word

To multiply 32-bit unsigned integers

Description:

(LO, HI) = GPR[rs] × GPR[rt]

The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating both operands as unsigned values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the high-order 32-bit word is placed into special register HI. The special register ACX is cleared.

No arithmetic exception occurs under any circumstances.

Restrictions:

None

Operation:

prod = (0 || GPR[rs]31..0) × (0 || GPR[rt]31..0)
LO = sign_extend(prod31..0)
HI = sign_extend(prod63..32)
ACX = 0

Exceptions:

None

Encoding:

Format:

PPERM rs, rt

Purpose:

Partial Permutation of Word Data into ACX-Hi-Lo Accumulator

Perform a partial permutation of a 32-bit value into the ACX/Hi/Lo registers

Description:

(LO, HI, ACX) = (LO, HI, ACX) << 6 | GPR[rs] bits specified by contents of GPR[rt]

The extended accumulator formed by the ACX, HI, and LO registers is shifted left by six bits, and 32-bit word value in GPR rt is used as a permutation descriptor to select a set of six bits from GPR rs, to be written into the least significant six bits of the LO register.

The contents of the rt register are interpreted as follows:

No arithmetic exception occurs under any circumstances.

Restrictions:

None

Operation:

TEMP = ACX(ACXBITS-6)..0 || HI31..26
ACX = TEMPACXBITS..0
TEMP = HI25..0 || LO31..26
HI = sign_extend(TEMP)
TEMP31...6 = LO25..0
BITSEL = GPR[rt]29..25
TEMP5 = GPR[rs]BITSEL
BITSEL = GPR[rt]24..20
TEMP4 = GPR[rs]BITSEL
BITSEL = GPR[rt]19..15
TEMP3 = GPR[rs]BITSEL
BITSEL = GPR[rt]14..10
TEMP2 = GPR[rs]BITSEL
BITSEL = GPR[rt]9..5
TEMP1 = GPR[rs]BITSEL
BITSEL = GPR[rt]4..0
TEMP0 = GPR[rs]BITSEL
LO = sign_extend(TEMP)

Exceptions:

None

Encoding:

Format:

ROTR rd, rt, sa

Purpose:

Rotate Word Right

To execute a logical right-rotate of a word by a fixed number of bits

Description:

GPR[rd] = GPR[rt] ↔ (right) sa

The contents ofthe low-order 32-bit word of GPR rt are rotated right;the word resultis placed in GPR rd. The bit-rotate amount is specified by sa.

Restrictions:

Operation:

if ((ArchitectureRevision() < 2) and (Config3SM = 0)) then
   UNPREDICTABLE
endif
s = sa
temp = GPR[rt]s-1..0 || GPR[rt]31..s
GPR[rd] = temp

Exceptions:

Reserved Instruction

Encoding:

Format:

ROTRV rd, rt, rs

Purpose:

Rotate Word Right Variable

To execute a logical right-rotate of a word by a variable number of bits

Description:

GPR[rd] = GPR[rt] ↔ (right) GPR[rs]

The contents ofthe low-order 32-bit word of GPR rt are rotated right;the word resultis placed in GPR rd. The bit-rotate amount is specified by the low-order 5 bits of GPR rs.

Restrictions:

Operation:

if ((ArchitectureRevision() < 2) and (Config3SM= 0)) then
   UNPREDICTABLE
endif
s = GPR[rs]4..0
temp = GPR[rt]s-1..0 || GPR[rt]31..s
GPR[rd] = temp

Exceptions:

Reserved Instruction