Encoding:

Format:

ADDS_A.df 

ADDS_A.B wd,ws,wt

ADDS_A.H wd,ws,wt

ADDS_A.W wd,ws,wt

ADDS_A.D wd,ws,wt

Purpose:

Vector Saturated Add of Absolute Values

Vector saturated addition to vector of absolute values.

Description:

wd[i] = saturate_signed(absolute_value(ws[i]) + absolute_value(wt[i]))

The absolute values of the elements in v ector wt are added to the absolute values of the elements in v ector ws. The saturated signed result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

ADDS_A.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = adds_a(WR[ws]8i+7..8i, WR[wt]8i+7..8i, 8)
   endfor
ADDS_A.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = adds_a(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 16)
   endfor
ADDS_A.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = adds_a(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
ADDS_A.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = adds_a(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function abs(tt, n)
   if ttn-1 = 1 then
      return -ttn-1...0
   else
      return ttn-1..0
   endif
endfunction abs
function sat_s(tt, n, b)
   if ttn-1 = 0 and ttn-1..b-1 != 0n-b+1 then
      return 0n-b+1 || 1b-1
   endif
   if ttn-1 = 1 and ttn-1..b-1 != 1n-b+1 then
      return 1n-b+1 || 0b-1
   else
      return tt
   endif
endfunction sat_s
function adds_a(ts, tt, n)
   t = (0 || abs(ts, n)) + (0 || abs(tt, n))
   return sat_s(t, n+1, n)
endfunction adds_a

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

ADDS_S.df 

ADDS_S.B wd,ws,wt

ADDS_S.H wd,ws,wt

ADDS_S.W wd,ws,wt

ADDS_S.D wd,ws,wt

Purpose:

Vector Signed Saturated Add of Signed Values

Vector addition to vector saturating the result as signed value.

Description:

wd[i] = saturate_signed(signed(ws[i]) + signed(wt[i]))

The elements in v ector wt are added to the ele ments in vector ws. Signed arithmetic is performed and overflows clamp to the largest and/or smallest representable signed values before writing the result to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

ADDS_S.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = adds_s(WR[ws]8i+7..8i, WR[wt]8i+7..8i, 8)
   endfor
ADDS_S.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = adds_s(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 16)
   endfor
ADDS_S.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = adds_s(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
ADDS_S.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = adds_s(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function sat_s(tt, n, b)
   if ttn-1 = 0 and ttn-1..b-1 != 0n-b+1 then
      return 0n-b+1 || 1b-1
   endif
   if ttn-1 = 1 and ttn-1..b-1 != 1n-b+1 then
      return 1n-b+1 || 0b-1
   else
      return tt
   endif
endfunction sat_s
function adds_s(ts, tt, n)
   t = (tsn-1 || ts) + (ttn-1 || tt)
   return sat_s(t, n+1, n)
endfunction adds_s

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

ADDS_U.df 

ADDS_U.B wd,ws,wt

ADDS_U.H wd,ws,wt

ADDS_U.W wd,ws,wt

ADDS_U.D wd,ws,wt

Purpose:

Vector Unsigned Saturated Add of Unsigned Values

Vector addition to vector saturating the result as unsigned value.

Description:

wd[i] = saturate_unsigned(unsigned(ws[i]) + unsigned(wt[i]))

The elements in v ector wt are added to the elements in vector ws. Unsigned arithmetic is performed and overflows clamp to the largest representable unsigned value before writing the result to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

ADDS_U.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = adds_u(WR[ws]8i+7..8i, WR[wt]8i+7..8i, 8)
   endfor
ADDS_U.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = adds_u(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 16)
   endfor
ADDS_U.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = adds_u(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
ADDS_U.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = adds_u(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function sat_u(tt, n, b)
   if ttn-1..b != 0n-b then
      return 0n-b || 1b
   else
      return tt
   endif
endfunction sat_u
function adds_u(ts, tt, n)
   t = (0 || ts) + (0 || tt)
   return sat_u(t, n+1, n)
endfunction adds_u

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

ADDV.df 

ADDV.B wd,ws,wt

ADDV.H wd,ws,wt

ADDV.W wd,ws,wt

ADDV.D wd,ws,wt

Purpose:

Vector Add

Vector addition to vector.

Description:

wd[i] = ws[i] + wt[i]

The elements in vector wt are added to the elements in vector ws. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

ADDV.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = WR[ws]8i+7..8i + WR[wt]8i+7..8i
   endfor
ADDV.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[ws]16i+15..16i + WR[wt]16i+15..16i
   endfor
ADDV.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[ws]32i+31..32i + WR[wt]32i+31..32i
   endfor
ADDV.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[ws]64i+63..64i + WR[wt]64i+63..64i
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

ADDVI.df 

ADDVI.B wd,ws,u5

ADDVI.H wd,ws,u5

ADDVI.W wd,ws,u5

ADDVI.D wd,ws,u5

Purpose:

Immediate Add

Immediate addition to vector.

Description:

wd[i] = ws[i] + u5

The 5-bit immediate unsigned value u5 is added to the elements in vector ws. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

ADDVI.B:
   t = 03 || u54..0
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = WR[ws]8i+7..8i + t
   endfor
ADDVI.H:
   t = 011 || u54..0
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[ws]16i+15..16i + t
   endfor
ADDVI.W:
   t = 027 || u54..0
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[ws]32i+31..32i + t
   endfor
ADDVI.D:
   t = 059 || u54..0
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[ws]64i+63..64i + t
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

ADD_A.df 

ADD_A.B wd,ws,wt

ADD_A.H wd,ws,wt

ADD_A.W wd,ws,wt

ADD_A.D wd,ws,wt

Purpose:

Vector Add Absolute Values

Vector addition to vector using the absolute values.

Description:

wd[i] = absolute_value(ws[i]) + absolute_value(wt[i])

The absolute values of the elements in v ector wt are added to the absolute values of the elements in v ector ws. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

ADD_A.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = abs(WR[ws]8i+7..8i, 8) + abs(WR[wt]8i+7..8i, 8)
   endfor
ADD_A.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = abs(WR[ws]16i+15..16i, 16) + abs(WR[wt]16i+15..16i, 16)
   endfor
ADD_A.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = abs(WR[ws]32i+31..32i, 32) + abs(WR[wt]32i+31..32i, 32)
   endfor
ADD_A.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = abs(WR[ws]64i+63..64i, 64) + abs(WR[wt]64i+63..64i, 64)
   endfor
function abs(tt, n)
   if ttn-1 = 1 then
      return -ttn-1...0
   else
      return ttn-1..0
   endif
endfunction abs

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

AND.V 

AND.V wd,ws,wt

Purpose:

Vector Logical And

Vector by vector logical and.

Description:

wd = ws AND wt

Each bit of vector ws is combined with the corresponding bit of vector wt in a bitwise logical AND operation. The result is written to vector wd.

The operands and results are bit vector values.

Restrictions:

No data-dependent exceptions are possible.

Operation:

 WR[wd] = WR[ws] and WR[wt]

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

ANDI.B 

ANDI.B wd,ws,i8

Purpose:

Immediate Logical And

Immediate by vector logical and.

Description:

wd[i] = ws[i] AND i8

Each byte element of vector ws is combined with the 8-bit immediate i8 in a bitwise logical AND operation. The result is written to vector wd.

The operands and results are values in integer byte data format.

Restrictions:

No data-dependent exceptions are possible.

Operation:

 for i in 0 .. WRLEN/8-1
   WR[wd]8i+7..8i = WR[ws]8i+7..8i and i87..0
endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

ASUB_S.df 

ASUB_S.B wd,ws,wt

ASUB_S.H wd,ws,wt

ASUB_S.W wd,ws,wt

ASUB_S.D wd,ws,wt

Purpose:

Vector Absolute Values of Signed Subtract

Vector subtraction from vector of signed values taking the absolute value of the results.

Description:

wd[i] = absolute_value(signed(ws[i]) - signed(wt[i]))

The signed elements in v ector wt are subtracted from the signed elements in v ector ws. The absolute value of the signed result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

ASUB_S.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = asub_s(WR[ws]8i+7..8i, WR[wt]8i+7..8i, 8)
   endfor
ASUB_S.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = asub_s(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 16)
   endfor
ASUB_S.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = asub_s(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
ASUB_S.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = asub_s(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function asub_s(ts, tt, n)
   t = (tsn-1 || ts) - (ttn-1 || tt)
   if tn = 0 then
      return tn-1..0
   else
      return (-t)n-1..0
endfunction asub_s

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

ASUB_U.df 

ASUB_U.B wd,ws,wt

ASUB_U.H wd,ws,wt

ASUB_U.W wd,ws,wt

ASUB_U.D wd,ws,wt

Purpose:

Vector Absolute Values of Unsigned Subtract

Vector subtraction from vector of unsigned values taking the absolute value of the results.

Description:

wd[i] = absolute_value(unsigned(ws[i]) - unsigned(wt[i]))

The unsigned elements in vector wt are subtracted from the unsigned elements in vector ws. The absolute value of the signed result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

ASUB_U.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = asub_u(WR[ws]8i+7..8i, WR[wt]8i+7..8i, 8)
   endfor
ASUB_U.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = asub_u(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 16)
   endfor
ASUB_U.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = asub_u(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
ASUB_U.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = asub_u(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function asub_u(ts, tt, n)
   t = (0 || ts) - (0 || tt)
   if tn = 0 then
      return tn-1..0
   else
      return (-t)n-1..0
endfunction asub_s

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

AVER_S.df 

AVER_S.B wd,ws,wt

AVER_S.H wd,ws,wt

AVER_S.W wd,ws,wt

AVER_S.D wd,ws,wt

Purpose:

Vector Signed Average Rounded

Vector average rounded using the signed values.

Description:

wd[i] = (ws[i] + wt[i] + 1) / 2

The elements in vector wt are added to the elements in vector ws. The addition of the elements plus 1 (for rounding) is done signed with full precision, i.e. the result has one extra bit. Signed division by 2 (or arithmetic shift right by one bit) is performed before writing the result to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

AVER_S.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = aver_s(WR[ws]8i+7..8i, WR[wt]8i+7..8i, 8)
   endfor
AVER_S.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = aver_s(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 16)
   endfor
AVER_S.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = aver_s(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
AVER_S.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = aver_s(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function ave_s(ts, tt, n)
   t = (tsn-1 || ts) + (ttn-1 || tt) + 1
   return tn..1
endfunction aver_s

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

AVER_U.df 

AVER_U.B wd,ws,wt

AVER_U.H wd,ws,wt

AVER_U.W wd,ws,wt

AVER_U.D wd,ws,wt

Purpose:

Vector Unsigned Average Rounded

Vector average rounded using the unsigned values.

Description:

wd[i] = (ws[i] + wt[i] + 1) / 2

The elements in vector wt are added to the elements in vector ws. The addition of the elements plus 1 (for rounding) is done unsigned with full precision, i.e. the result has one extra bit. Unsigned division by 2 (or logical shift right by one bit) is performed before writing the result to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

AVER_U.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = aver_u(WR[ws]8i+7..8i, WR[wt]8i+7..8i, 8)
   endfor
AVER_U.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = aver_u(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 16)
   endfor
AVER_U.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = aver_u(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
AVER_U.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = aver_u(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function ave_u(ts, tt, n)
   t = (0 || ts) + (0 || tt) + 1
   return tn..1
endfunction aver_u

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

AVE_S.df 

AVE_S.B wd,ws,wt

AVE_S.H wd,ws,wt

AVE_S.W wd,ws,wt

AVE_S.D wd,ws,wt

Purpose:

Vector Signed Average

Vector average using the signed values.

Description:

wd[i] = (ws[i] + wt[i]) / 2

The elements in vector wt are added to the elements in vector ws. The addition is done signed with full precision, i.e. the result has one extra bit. Signed division by 2 (or arithmetic shift right by one bit) is performed before writing the result to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

AVE_S.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = ave_s(WR[ws]8i+7..8i, WR[wt]8i+7..8i, 8)
   endfor
AVE_S.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = ave_s(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 16)
   endfor
AVE_S.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = ave_s(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
AVE_S.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = ave_s(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function ave_s(ts, tt, n)
   t = (tsn-1 || ts) + (ttn-1 || tt)
   return tn..1
endfunction ave_s

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

AVE_U.df 

AVE_U.B wd,ws,wt

AVE_U.H wd,ws,wt

AVE_U.W wd,ws,wt

AVE_U.D wd,ws,wt

Purpose:

Vector Unsigned Average

Vector average using the unsigned values.

Description:

wd[i] = (ws[i] + wt[i]) / 2

The elements in vector wt are added to the elements in vector ws. The addition is done unsigned with full precision, i.e. the result has one extra bit. Unsigned division by 2 (or logical shift right by one bit) is performed before writing the result to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

AVE_U.B:
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = ave_u(WR[ws]8i+7..8i, WR[wt]8i+7..8i, 8)
   endfor
AVE_U.H:
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = ave_u(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 16)
   endfor
AVE_U.W:
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = ave_u(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
AVE_U.D:
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = ave_u(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function ave_u(ts, tt, n)
   t = (0 || ts) + (0 || tt)
   return tn..1
endfunction ave_u

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BCLR.df 

BCLR.B wd,ws,wt

BCLR.H wd,ws,wt

BCLR.W wd,ws,wt

BCLR.D wd,ws,wt

Purpose:

Vector Bit Clear

Vector selected bit position clear in each element.

Description:

wd[i] = bit_clear(ws[i], wt[i])

Clear (set to 0) one bit in each element of vector ws. The bit position is given by the elements in wt modulo the size of the element in bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BCLR.B:
   for i in 0 .. WRLEN/8-1
      t = WR[wt]8i+2..8i
      WR[wd]8i+7..8i = WR[ws]8i+7..8i and (17-t || 0 || 1t)
   endfor
BCLR.:
   for i in 0 .. WRLEN/16-1
      t = WR[wt]16i+3..16i
      WR[wd]16i+15..16i = WR[ws]16i+15..16i and (115-t || 0 || 1t)
   endfor
BCLR.W:
   for i in 0 .. WRLEN/32-1
      t = WR[wt]32i+4..32i
      WR[wd]32i+31..32i = WR[ws]32i+31..32i and (131-t || 0 || 1t)
   endfor
BCLR.D:
   for i in 0 .. WRLEN/64-1
      t = WR[wt]64i+5..64i
      WR[wd]64i+63..64i = WR[ws]64i+63..64i and (163-t || 0 || 1t)
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BCLRI.df 

BCLRI.B wd,ws,m

BCLRI.H wd,ws,m

BCLRI.W wd,ws,m

BCLRI.D wd,ws,m

Purpose:

Immediate Bit Clear

Immediate selected bit position clear in each element.

Description:

wd[i] = bit_clear(ws[i], m)

Clear (set to 0) one bit in each element of vector ws. The bit position is given by the immediate m modulo the size of the element in bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BCLRI.B:
   t = m
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = WR[ws]8i+7..8i and (17-t || 0 || 1t)
   endfor
BCLRI.H:
   t = m
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[ws]16i+15..16i and (115-t || 0 || 1t)
   endfor
BCLRI.W:
   t = m
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[ws]32i+31..32i and (131-t || 0 || 1t)
   endfor
BCLRI.D:
   t = m
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[ws]64i+63..64i and (163-t || 0 || 1t)
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BINSL.df 

BINSL.B wd,ws,wt

BINSL.H wd,ws,wt

BINSL.W wd,ws,wt

BINSL.D wd,ws,wt

Purpose:

Vector Bit Insert Left

Vector selected left most bits copy while preserving destination right bits.

Description:

wd[i] = bit_insert_left(wd[i], ws[i], wt[i])

Copy most significant (left) bits in each element of vector ws to elements in vector wd while preserving the least significant (right) bits. The number of bits to copy is given by the elements in vector wt modulo the size of the element in bits plus 1.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BINSL.B:
   for i in 0 .. WRLEN/8-1
      t = WR[wt]8i+2..8i
      WR[wd]8i+7..8i = WR[ws]8i+7..8i+7-t || WR[wd]8i+7-t-1..8i
   endfor
BINSL.H:
   for i in 0 .. WRLEN/16-1
      t = WR[wt]16i+3..16i
      WR[wd]16i+15..16i = WR[ws]16i+15..16i+15-t || WR[wd]16i+15-t-1..16i
   endfor
BINSL.W:
   for i in 0 .. WRLEN/32-1
      t = WR[wt]32i+4..32i
      WR[wd]32i+31..32i = WR[ws]32i+31..32i+31-t || WR[wd]32i+31-t-1..32i
   endfor
BINSL.D:
   for i in 0 .. WRLEN/64-1
      t = WR[wt]64i+5..64i
      WR[wd]64i+63..64i = WR[ws]64i+63..64i+63-t || WR[wd]64i+63-t-1..64i
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BINSLI.df 

BINSLI.B wd,ws,m

BINSLI.H wd,ws,m

BINSLI.W wd,ws,m

BINSLI.D wd,ws,m

Purpose:

Immediate Bit Insert Left

Immediate selected left most bits copy while preserving destination right bits.

Description:

wd[i] = bit_insert_left(wd[i], ws[i], m)

Copy most significant (left) bits in each element of vector ws to elements in vector wd while preserving the least significant (right) bits. The number of bits to copy is given by the immediate m modulo the size of the element in bits plus 1.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BINSLI.B:
   t = m
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = WR[ws]8i+7..8i+7-t || WR[wd]8i+7-t-1..8i
   endfor
BINSLI.H:
   t = m
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[ws]16i+15..16i+15-t || WR[wd]16i+15-t-1..16i
   endfor
BINSLI.W:
   t = m
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[ws]32i+31..32i+31-t || WR[wd]32i+31-t-1..32i
   endfor
BINSLI.D:
   t = m
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[ws]64i+63..64i+63-t || WR[wd]64i+63-t-1..64i
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BINSR.df 

BINSR.B wd,ws,wt

BINSR.H wd,ws,wt

BINSR.W wd,ws,wt

BINSR.D wd,ws,wt

Purpose:

Vector Bit Insert Right

Vector selected right most bits copy while preserving destination left bits.

Description:

wd[i] = bit_insert_right(wd[i], ws[i], wt[i])

Copy least significant (right) bits in each element of vector ws to elements in vector wd while preserving the most significant (left) bits. The number of bits to copy is given by the elements in vector wt modulo the size of the element in bits plus 1.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BINSR.B:
   for i in 0 .. WRLEN/8-1
      t = WR[wt]8i+2..8i
      WR[wd]8i+7..8i = WR[wd]8i+7..8i+t+1 || WR[ws]8i+t..8i
   endfor
BINSR.H:
   for i in 0 .. WRLEN/16-1
      t = WR[wt]16i+3..16i
      WR[wd]16i+15..16i = WR[wd]16i+15..16i+t+1 || WR[ws]16i+t..16i
   endfor
BINSR.W:
   for i in 0 .. WRLEN/32-1
      t = WR[wt]32i+4..32i
      WR[wd]32i+31..32i = WR[wd]32i+31..32i+t+1 || WR[ws]32i+t..32i
   endfor
BINSR.D:
   for i in 0 .. WRLEN/64-1
      t = WR[wt]64i+5..64i
      WR[wd]64i+63..64i = WR[wd]64i+63..64i+t+1 || WR[ws]64i+t..64i
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BINSRI.df 

BINSRI.B wd,ws,m

BINSRI.H wd,ws,m

BINSRI.W wd,ws,m

BINSRI.D wd,ws,m

Purpose:

Immediate Bit Insert Right

Immediate selected right most bits copy while preserving destination left bits.

Description:

wd[i] = bit_insert_right(wd[i], ws[i], m)

Copy least significant (right) bits in each element of vector ws to elements in vector wd while preserving the most significant (left) bits. The number of bits to copy is given by the immediate m modulo the size of the element in bits plus

1.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BINSRI.B:
   t = m
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = WR[wd]8i+7..8i+7+t+1 || WR[ws]8i+t..8i
   endfor
BINSRI.H:
   t = m
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[wd]16i+15..16i+t+1 || WR[ws]16i+t..16i
   endfor
BINSRI.W:
   t = m
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[wd]32i+31..32i+t+1 || WR[ws]32i+t..32i
   endfor
BINSRI.D:
   t = m
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[wd]64i+63..64i+t+1 || WR[ws]64i+t..64i
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BMNZ.V 

BMNZ.V wd,ws,wt

Purpose:

Vector Bit Move If Not Zero

Vector mask-based copy bits on the condition mask being set.

Description:

wd = (ws AND wt) OR (wd AND NOT wt)

Copy to destination vector wd all bits from source v ector ws for which the corresponding bits from target vector wt are 1 and leaves unchanged all destination bits for which the corresponding target bits are 0.

The operands and results are bit vector values.

Restrictions:

No data-dependent exceptions are possible.

Operation:

 WR[wd] = (WR[ws] and WR[wt]) or (WR[wd] and not WR[wt])

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BMNZI.B 

BMNZI.B wd,ws,i8

Purpose:

Immediate Bit Move If Not Zero

Immediate mask-based copy bits on the condition mask being set.

Description:

wd[i] = (ws[i] AND i8) OR (wd[i] AND NOT i8)

Copy to destination vector wd all bits from source vector ws for which the corresponding bits from immediate i8 are 1 and leaves unchanged all destination bits for which the corresponding immediate bits are 0.

The operands and results are vector values in integer byte data format.

Restrictions:

No data-dependent exceptions are possible.

Operation:

 WR[wd] = (WR[ws]8i+7..8i and i87..0) or (WR[wd]8i+7..8i and not i87..0)

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BMZ.V 

BMZ.V wd,ws,wt

Purpose:

Vector Bit Move If Zero

Vector mask-based copy bits on the condition mask being clear.

Description:

wd = (ws AND NOT wt) OR (wd AND wt)

Copy to destination vector wd all bits from source v ector ws for which the corresponding bits from target vector wt are 0 and leaves unchanged all destination bits for which the corresponding target bits are 1.

The operands and results are bit vector values.

Restrictions:

No data-dependent exceptions are possible.

Operation:

 WR[wd] = (WR[ws] and not WR[wt]) or (WR[wd] and WR[wt])

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BMZI.B 

BMZI.B wd,ws,i8

Purpose:

Immediate Bit Move If Zero

Immediate mask-based copy bits on the condition mask being clear.

Description:

wd[i] = (ws[i] AND NOT i8) OR (wd[i] AND i8)

Copy to destination vector wd all bits from source vector ws for which the corresponding bits from immediate i8 are 0 and leaves unchanged all destination bits for which the corresponding immediate bits are 1.

The operands and results are vector values in integer byte data format.

Restrictions:

No data-dependent exceptions are possible.

Operation:

 WR[wd] = (WR[ws] and not i87..0) or (WR[wd] and i87..0)

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BNEG.df 

BNEG.B wd,ws,wt

BNEG.H wd,ws,wt

BNEG.W wd,ws,wt

BNEG.D wd,ws,wt

Purpose:

Vector Bit Negate

Vector selected bit position negate in each element.

Description:

wd[i] = bit_negate(ws[i], wt[i])

Negate (complement) one bit in each element of vector ws. The bit position is given by the elements in wt modulo the size of the element in bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BNEG.B:
   for i in 0 .. WRLEN/8-1
      t = WR[wt]8i+2..8i
      WR[wd]8i+7..8i = WR[ws]8i+7..8i xor (07-t || 1 || 0t)
   endfor
BNEG.H:
   for i in 0 .. WRLEN/16-1
      t = WR[wt]16i+3..16i
      WR[wd]16i+15..16i = WR[ws]16i+15..16i xor (015-t || 1 || 0t)
   endfor
BNEG.W:
   for i in 0 .. WRLEN/32-1
      t = WR[wt]32i+4..32i
      WR[wd]32i+31..32i = WR[ws]32i+31..32i xor (031-t || 1 || 0t)
   endfor
BNEG.D:
   for i in 0 .. WRLEN/64-1
      t = WR[wt]64i+5..64i
      WR[wd]64i+63..64i = WR[ws]64i+63..64i xor (063-t || 1 || 0t)
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BNEGI.df 

BNEGI.B wd,ws,m

BNEGI.H wd,ws,m

BNEGI.W wd,ws,m

BNEGI.D wd,ws,m

Purpose:

Immediate Bit Negate

Immediate selected bit position negate in each element.

Description:

wd[i] = bit_negate(ws[i], m)

Negate (complement) one bit in each element of vector ws. The bit position is given by the immediate m modulo the size of the element in bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BNEGI.B:
   t = m
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = WR[ws]8i+7..8i xor (07-t || 1 || 0t)
   endfor
BNEGI.H:
   t = m
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[ws]16i+15..16i xor (015-t || 1 || 0t)
   endfor
BNEGI.W:
   t = m
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[ws]32i+31..32i xor (031-t || 1 || 0t)
   endfor
BNEGI.D:
   t = m
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[ws]64i+63..64i xor (063-t || 1 || 0t)
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BNZ.df 

BNZ.B wt,s16

BNZ.H wt,s16

BNZ.W wt,s16

BNZ.D wt,s16

Purpose:

Immediate Branch If All Elements Are Not Zero

Immediate PC offset branch if all destination elements are not zero.

Description:

if wt[i] != 0 for all i then branch PC-relative s16

PC-relative branch if all elements in wt are not zero. The branch instruction has a delay slot. s16 is a PC word offset, i.e. signed count of 32-bit instructions, from the PC of the delay slot.

Restrictions:

Processor operation is UNPREDICTABLE if a branch is placed in the delay slot of a branch or jump.

Operation:

BNZ.B:
   branch(WR[wt]8i+7..8i != 0 for all i, s16)
BNZ.H:
   branch(WR[wt]16i+15..16i != 0 for all i, s16)
BNZ.W:
   branch(WR[wt]32i+31..32i != 0 for all i, s16)
BNZ.D:
   branch(WR[wt]64i+63..64i != 0 for all i, s16)
function branch(cond, offset)
   if cond then
      I:   target_offset = (offset9)GPRLEN-12 || offset9..0 || 0^^2
      I+1: PC = PC + target_offset
   endif
endfunction branch

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BNZ.V 

BNZ.V wt,s16

Purpose:

Immediate Branch If Not Zero (At Least One Element of Any Format Is Not Zero)

Immediate PC offset branch if destination vector is not zero.

Description:

if wt != 0 then branch PC-relative s16

PC-relative branch if at least one bit in wt is not zero, i.e at least one element is not zero regardless of the data format. The branch instruction has a delay slot. s16 is a PC word offset, i.e. signed count of 32-bit instructions, from the PC of the delay slot.

Restrictions:

Processor operation is UNPREDICTABLE if a branch is placed in the delay slot of a branch or jump.

Operation:

   branch(WR[wt] != 0, s16)
function branch(cond, offset)
   if cond then
      I:   target_offset = (offset9)GPRLEN-12 || offset9..0 || 0^^2
      I+1: PC = PC + target_offset
   endif
endfunction branch

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BSEL.V 

BSEL.V wd,ws,wt

Purpose:

Vector Bit Select

Vector mask-based copy bits from two source vectors selected by the bit mask value

Description:

wd = (ws AND NOT wd) OR (wt AND wd)

Selectively copy bits from the source v ectors ws and wt into destination vector wd based on the corresponding bit in wd: if 0 copies the bit from ws, if 1 copies the bit from wt.

Restrictions:

The operands and results are bit vector values.

Operation:

 WR[wd] = (WR[ws] and not WR[wd]) or (WR[wt] and WR[wd])

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BSELI.B 

BSELI.B wd,ws,i8

Purpose:

Immediate Bit Select

Immediate mask-based copy bits from two source vectors selected by the bit mask value

Description:

wd = (ws AND NOT wd) OR (i8 AND wd)

Selectively copy bits from the the 8-bit immediate i8 and source v ector ws into destination vector wd based on the corresponding bit in wd: if 0 copies the bit from ws, if 1 copies the bit from i8.

Restrictions:

The operands and results are bit vector values.

Operation:

 for i in 0 .. WRLEN/8-1
   WR[wd]8i+7..8i =
      (WR[ws]8i+7..8i and not WR[wd]8i+7..8i) or (i87..0 and WR[wd]8i+7..8i)
endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BSET.df 

BSET.B wd,ws,wt

BSET.H wd,ws,wt

BSET.W wd,ws,wt

BSET.D wd,ws,wt

Purpose:

Vector Bit Set

Vector selected bit position set in each element.

Description:

wd[i] = bit_set(ws[i], wt[i])

Set to 1 one bit in each element of v ector ws. The bit position is given by the elements in wt modulo the size of the element in bits. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BSET_S.B:
   for i in 0 .. WRLEN/8-1
      t = WR[wt]8i+2..8i
      WR[wd]8i+7..8i = WR[ws]8i+7..8i or (07-t || 1 || 0t)
   endfor
BSET_S.H:
   for i in 0 .. WRLEN/16-1
      t = WR[wt]16i+3..16i
      WR[wd]16i+15..16i = WR[ws]16i+15..16i or (015-t || 1 || 0t)
   endfor
BSET_S.W:
   for i in 0 .. WRLEN/32-1
      t = WR[wt]32i+4..32i
      WR[wd]32i+31..32i = WR[ws]32i+31..32i or (031-t || 1 || 0t)
   endfor
BSET_S.D:
   for i in 0 .. WRLEN/64-1
      t = WR[wt]64i+5..64i
      WR[wd]64i+63..64i = WR[ws]64i+63..64i or (063-t || 1 || 0t)
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BSETI.df 

BSETI.B wd,ws,m

BSETI.H wd,ws,m

BSETI.W wd,ws,m

BSETI.D wd,ws,m

Purpose:

Immediate Bit Set

Immediate selected bit position set in each element.

Description:

wd[i] = bit_set(ws[i], m)

Set to 1 one bit in each element of vector ws. The bit position is given by the immediate m. The result is written to vector wd.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

BSETI_S.B:
   t = m
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = WR[ws]8i+7..8i or (07-t || 1 || 0t)
   endfor
BSETI_S.H:
   t = m
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[ws]16i+15..16i or (015-t || 1 || 0t)
   endfor
BSETI_S.W:
   t = m
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[ws]32i+31..32i or (031-t || 1 || 0t)
   endfor
BSETI_S.D:
   t = m
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[ws]64i+63..64i or (063-t || 1 || 0t)
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BZ.df 

BZ.B wt,s16

BZ.H wt,s16

BZ.W wt,s16

BZ.D wt,s16

Purpose:

Immediate Branch If At Least One Element Is Zero

Immediate PC offset branch if at least one destination element is zero.

Description:

if wt[i] = 0 for some i then branch PC-relative s16

PC-relative branch if at least one element in wt is zero. The branch instruction has a delay slot. s16 is a PC word offset, i.e. signed count of 32-bit instructions, from the PC of the delay slot.

Restrictions:

Processor operation is UNPREDICTABLE if a branch is placed in the delay slot of a branch or jump.

Operation:

BZ.B:
   for i in 0 .. WRLEN/8-1
      branch(WR[wt]8i+7..8i = 0, s16)
   endfor
BZ.H:
   for i in 0 .. WRLEN/16-1
      branch(WR[wt]16i+15..16i = 0, s16)
   endfor
BZ.W:
   for i in 0 .. WRLEN/32-1
      branch(WR[wt]32i+31..32i = 0, s16)
   endfor
BZ.D:
   for i in 0 .. WRLEN/64-1
      branch(WR[wt]64i+63..64i = 0, s16)
   endfor
function branch(cond, offset)
   if cond then
      I:   target_offset = (offset9)GPRLEN-12 || offset9..0 || 0^^2
      I+1: PC = PC + target_offset
   endif
endfunction branch

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

BZ.V 

BZ.V wt,s16

Purpose:

Immediate Branch If Zero (All Elements of Any Format Are Zero)

Immediate PC offset branch if destination vector is zero.

Description:

if wt = 0 then branch PC-relative s16

PC-relative branch if all wt bits are zero, i.e. all elements are zero regardless of the data format. The branch instruction has a delay slot. s16 is a PC word offset, i.e. signed count of 32-bit instructions, from the PC of the delay slot.

Restrictions:

Processor operation is UNPREDICTABLE if a branch is placed in the delay slot of a branch or jump.

Operation:

   branch(WR[wt] = 0, s16)
function branch(cond, offset)
   if cond then
      I:   target_offset = (offset9)GPRLEN-12 || offset9..0 || 0^^2
      I+1: PC = PC + target_offset
   endif
endfunction branch

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CEQ.df 

CEQ.B wd,ws,wt

CEQ.H wd,ws,wt

CEQ.W wd,ws,wt

CEQ.D wd,ws,wt

Purpose:

Vector Compare Equal

Vector to vector compare for equality; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] = wt[i])

Set all bits to 1 in wd elements if the corresponding ws and wt elements are equal, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CEQ.B:
   for i in 0 .. WRLEN/8-1
      c = WR[ws]8i+7..8i = WR[wt]8i+7..8i
      WR[wd]8i+7..8i = c8
   endfor
CEQ.H:
   for i in 0 .. WRLEN/16-1
      c = WR[ws]16i+15..16i = WR[wt]16i+15..16i
      WR[wd]16i+15..16i = c16
   endfor
CEQ.W:
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i = WR[wt]32i+31..32i
      WR[wd]32i+31..32i = c32
   endfor
CEQ.D:
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i = WR[wt]64i+63..64i
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CEQI.df 

CEQI.B wd,ws,s5

CEQI.H wd,ws,s5

CEQI.W wd,ws,s5

CEQI.D wd,ws,s5

Purpose:

Immediate Compare Equal

Immediate to vector compare for equality; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] = s5)

Set all bits to 1 in wd elements if the corresponding ws element and the 5-bit signed immediate s5 are equal, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CEQI.B:
   t = (s54)3 || s54..0
   for i in 0 .. WRLEN/8-1
      c = WR[ws]8i+7..8i = t
      WR[wd]8i+7..8i = c8
   endfor
CEQI.H:
   t = (s54)11 || s54..0
   for i in 0 .. WRLEN/16-1
      c = WR[ws]16i+15..16i = t
      WR[wd]16i+15..16i = c16
   endfor
CEQI.W:
   t = (s54)27 || s54..0
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i = t
      WR[wd]32i+31..32i = c32
   endfor
CEQI.D:
   t = (s54)59 || s54..0
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i = t
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CFCMSA 

CFCMSA rd,cs

Purpose:

GPR Copy from MSA Control Register

GPR value copied from MSA control register.

Description:

rd = signed(cs)

The sign extended content of MSA control register cs is copied to GPR rd.

Restrictions:

The read operation returns ZERO if cs specifies a reserved register or a register that does not exist.

Operation:

if cs = 0 then
   GPR[rd] = sign_extend(MSAIR, 64)
elseif cs = 1 then
   GPR[rd] = sign_extend(MSACSR, 64)
elseif MSAIRWRP = 1 then
   if cs = 2 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      GPR[rd] = sign_extend(MSAAccess, 64)
   elseif cs = 3 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      GPR[rd] = sign_extend(MSASave, 64)
   elseif cs = 4 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      GPR[rd] = sign_extend(MSAModify, 64)
   elseif cs = 5 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      GPR[rd] = sign_extend(MSARequest, 64)
   elseif cs = 6 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      GPR[rd] = sign_extend(MSAMap, 64)
   elseif cs = 7 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      GPR[rd] = sign_extend(MSAUnmap, 64)
   else
      GPR[rd] = 0
   endif
else
   GPR[rd] = 0
endif

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception. Coprocessor 0 Unusable Exception.

Encoding:

Format:

CLEI_S.df 

CLEI_S.B wd,ws,s5

CLEI_S.H wd,ws,s5

CLEI_S.W wd,ws,s5

CLEI_S.D wd,ws,s5

Purpose:

Immediate Compare Signed Less Than or Equal

Immediate to vector compare for signed less or equal; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] <= s5)

Set all bits to 1 in wd elements if the corresponding ws element is less than or equal to the 5-bit signed immediate s5, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLEI_S.B
   t = (s54)3 || s54..0
   for i in 0 .. WRLEN/8-1
      c = WR[ws]8i+7..8i <= t
      WR[wd]8i+7..8i = c8
   endfor
CLEI_S.H
   t = (s54)11 || s54..0
   for i in 0 .. WRLEN/16-1
      c = WR[ws]16i+15..16i <= t
      WR[wd]16i+15..16i = c16
   endfor
CLEI_S.W
   t = (s54)27 || s54..0
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i <= t
      WR[wd]32i+31..32i = c32
   endfor
CLEI_S.D
   t = (s54)59 || s5__4.. 0__
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i <= t
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CLEI_U.df 

CLEI_U.B wd,ws,u5

CLEI_U.H wd,ws,u5

CLEI_U.W wd,ws,u5

CLEI_U.D wd,ws,u5

Purpose:

Immediate Compare Unsigned Less Than or Equal

Immediate to vector compare for unsigned less or equal; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] <= u5)

Set all bits to 1 in wd elements if the corresponding ws element is unsigned less than or equal to the 5-bit unsigned immediate u5, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLEI_U.B
   t = 03 || u54..0
   for i in 0 .. WRLEN/8-1
      c = (0 || WR[ws]8i+7..8i) <= (0 || t)
      WR[wd]8i+7..8i = c8
   endfor
CLEI_U.H
   t = 011 || u54..0
   for i in 0 .. WRLEN/16-1
      c = (0 || WR[ws]16i+15..16i) <= (0 || t)
      WR[wd]16i+15..16i = c16
   endfor
CLEI_U.W
   t = 027 || u54..0
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i <= (0 || t)
      WR[wd]32i+31..32i = c32
   endfor
CLEI_U.D
   t = 059 || u54..0
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i <= (0 || t)
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CLE_S.df 

CLE_S.B wd,ws,wt

CLE_S.H wd,ws,wt

CLE_S.W wd,ws,wt

CLE_S.D wd,ws,wt

Purpose:

Vector Compare Signed Less Than or Equal

Vector to vector compare for signed less or equal; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] <= wt[i])

Set all bits to 1 in wd elements if the corresponding ws elements are signed less than or equal to wt elements, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLE_S.B:
   for i in 0 .. WRLEN/8-1
      c = WR[ws]8i+7..8i <= WR[wt]8i+7..8i
      WR[wd]8i+7..8i = c8
   endfor
CLE_S.H:
   for i in 0 .. WRLEN/16-1
      c = WR[ws]16i+15..16i <= WR[wt]16i+15..16i
      WR[wd]16i+15..16i = c16
   endfor
CLE_S.W:
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i <= WR[wt]32i+31..32i
      WR[wd]32i+31..32i = c32
   endfor
CLE_S.D:
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i <= WR[wt]64i+63..64i
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CLE_U.df 

CLE_U.B wd,ws,wt

CLE_U.H wd,ws,wt

CLE_U.W wd,ws,wt

CLE_U.D wd,ws,wt

Purpose:

Vector Compare Unsigned Less Than or Equal

Vector to vector compare for unsigned less or equal; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] <= wt[i])

Set all bits to 1 in wd elements if the corresponding ws elements are unsigned less than or equal to wt elements, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLE_U.B
   for i in 0 .. WRLEN/8-1
      c = (0 || WR[ws]8i+7..8i) <= (0 || WR[wt]8i+7..8i)
      WR[wd]8i+7..8i = c8
   endfor
CLE_U.H
   for i in 0 .. WRLEN/16-1
      c = (0 || WR[ws]16i+15..16i) <= (0 || WR[wt]16i+15..16i)
      WR[wd]16i+15..16i = c16
   endfor
CLE_U.W
   for i in 0 .. WRLEN/32-1
      c = (0 || WR[ws]__32i+31..32i_)_ <= (0 || WR[wt]32i+31..32i)
      WR[wd]32i+31..32i = c32
   endfor
CLE_U.D
   for i in 0 .. WRLEN/64-1
      c = (0 || WR[ws]64i+63..64i) <= (0 || WR[wt]64i+63..64i)
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CLTI_S.df 

CLTI_S.B wd,ws,s5

CLTI_S.H wd,ws,s5

CLTI_S.W wd,ws,s5

CLTI_S.D wd,ws,s5

Purpose:

Immediate Compare Signed Less Than

Immediate to vector compare for signed less than; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] < s5)

Set all bits to 1 in wd elements if the corresponding ws element is less than the 5-bit signed immediate s5, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLTI_S.B
   t = (s54)3 || s54..0
   for i in 0 .. WRLEN/8-1
      c = WR[ws]8i+7..8i < t
      WR[wd]8i+7..8i = c8
   endfor
CLTI_S.H
   t = (s54)11 || s54..0
   for i in 0 .. WRLEN/16-1
      c = WR[ws]16i+15..16i < t
      WR[wd]16i+15..16i = c16
   endfor
CLTI_S.W
   t = (s54)27 || s54..0
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i < t
      WR[wd]32i+31..32i = c32
   endfor
CLTI_S.D
   t = (s54)59 || s5__4.. 0__
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i < t
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CLTI_U.df 

CLTI_U.B wd,ws,u5

CLTI_U.H wd,ws,u5

CLTI_U.W wd,ws,u5

CLTI_U.D wd,ws,u5

Purpose:

Immediate Compare Unsigned Less Than

Immediate to vector compare for unsigned less than; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] < u5)

Set all bits to 1 in wd elements if the corresponding ws element is unsigned less than the 5-bit unsigned immediate u5, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLTI_U.B
   t = 03 || u54..0
   for i in 0 .. WRLEN/8-1
      c = (0 || WR[ws]8i+7..8i) < (0 || t)
      WR[wd]8i+7..8i = c8
   endfor
CLTI_U.H
   t = 011 || u54..0
   for i in 0 .. WRLEN/16-1
      c = (0 || WR[ws]16i+15..16i) < (0 || t)
      WR[wd]16i+15..16i = c16
   endfor
CLTI_U.W
   t = 027 || u54..0
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i < (0 || t)
      WR[wd]32i+31..32i = c32
   endfor
CLTI_U.D
   t = 059 || u54..0
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i < (0 || t)
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CLT_S.df 

CLT_S.B wd,ws,wt

CLT_S.H wd,ws,wt

CLT_S.W wd,ws,wt

CLT_S.D wd,ws,wt

Purpose:

Vector Compare Signed Less Than

Vector to vector compare for signed less than; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] < wt[i])

Set all bits to 1 i n wd elements if the corresponding ws elements are signed less than wt elements, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLT_S.B
   for i in 0 .. WRLEN/8-1
      c = WR[ws]8i+7..8i < WR[wt]8i+7..8i
      WR[wd]8i+7..8i = c8
   endfor
CLT_S.H
   for i in 0 .. WRLEN/16-1
      c = WR[ws]16i+15..16i < WR[wt]16i+15..16i
      WR[wd]16i+15..16i = c16
   endfor
CLT_S.W
   for i in 0 .. WRLEN/32-1
      c = WR[ws]32i+31..32i < WR[wt]32i+31..32i
      WR[wd]32i+31..32i = c32
   endfor
CLT_S.D
   for i in 0 .. WRLEN/64-1
      c = WR[ws]64i+63..64i < WR[wt]64i+63..64i
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CLT_U.df 

CLT_U.B wd,ws,wt

CLT_U.H wd,ws,wt

CLT_U.W wd,ws,wt

CLT_U.D wd,ws,wt

Purpose:

Vector Compare Unsigned Less Than

Vector to vector compare for unsigned less than; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] < wt[i])

Set all bits to 1 in wd elements if the corresponding ws elements are unsigned less than wt elements, otherwise set all bits to 0.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

CLT_U.B
   for i in 0 .. WRLEN/8-1
      c = (0 || WR[ws]8i+7..8i) < (0 || WR[wt]8i+7..8i)
      WR[wd]8i+7..8i = c8
   endfor
CLT_U.H
   for i in 0 .. WRLEN/16-1
      c = (0 || WR[ws]16i+15..16i) < (0 || WR[wt]16i+15..16i)
      WR[wd]16i+15..16i = c16
   endfor
CLT_U.W
   for i in 0 .. WRLEN/32-1
      c = (0 || WR[ws]__32i+31..32i_)_ < (0 || WR[wt]32i+31..32i)
      WR[wd]32i+31..32i = c32
   endfor
CLT_U.D
   for i in 0 .. WRLEN/64-1
      c = (0 || WR[ws]64i+63..64i) < (0 || WR[wt]64i+63..64i)
      WR[wd]64i+63..64i = c64
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

COPY_S.df 

COPY_S.B rd,ws[n]

COPY_S.H rd,ws[n]

COPY_S.W rd,ws[n]

COPY_S.D rd,ws[n]

Purpose:

Element Copy to GPR Signed

Element value sign extended and copied to GPR.

Description:

rd = signed(ws[n])

Sign-extend element n of vector ws and copy the result to GPR rd.

Restrictions:

No data-dependent exceptions are possible.

Operation:

COPY_S.B
   GPR[rd] = sign_extend(WR[ws]8n+7..8n, 64)
COPY_S.H
   GPR[rd] = sign_extend(WR[ws]16n+15..16n, 64)
COPY_S.W
   GPR[rd] = sign_extend(WR[ws]32n+31..32n, 64)
COPY_S.D
   GPR[rd] = WR[ws]64n+63..64n
function sign_extend(tt, n)
   return (ttn-1)GPRLEN-n || ttn-1..0
endfunction sign_extend

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

COPY_U.df 

COPY_U.B rd,ws[n]

COPY_U.H rd,ws[n]

COPY_U.W rd,ws[n]

Purpose:

Element Copy to GPR Unsigned

Element value zero extended and copied to GPR.

Description:

rd = unsigned(ws[n])

Zero-extend element n of vector ws and copy the result to GPR rd.

Restrictions:

No data-dependent exceptions are possible.

Operation:

COPY_U.B
   GPR[rd] = zero_extend(WR[ws]8n+7..8n, 64))
COPY_U.H
   GPR[rd] = zero_extend(WR[ws]16n+15..16n, 64))
COPY_U.W
   GPR[rd] = zero_extend(WR[ws]32n+31..32n, 64)
function zero_extend(tt, n)
   return 0GPRLEN-n || ttn-1..0
endfunction zero_extend

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

CTCMSA 

CTCMSA cd,rs

Purpose:

GPR Copy to MSA Control Register

GPR value copied to MSA control register.

Description:

cd = rs

The content of the least significant 31 bits of GPR rs is copied to MSA control register cd.

Writing to the MSA Control and Status Register MSACSR causes the appropriate e xception if any Cause bit and its corresponding Enable bit are both set. The register is written before the exception occurs and the EPC register contains the address of the CTCMSA instruction.

Restrictions:

The write attempt is IGNORED if cd specifies a reserved register or a register that does not exist or is not writable.

Operation:

if cd = 1 then
   MSACSR = GPR[rs]31..0
   if MSACSRCause and (1 || MSACSREnables) != 0 then
      SignalException(MSAFloatingPointException)
   endif
elseif MSAIRWRP = 1 then
   if cd = 3 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      MSASave = GPR[rs]31..0
   elseif cd = 4 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      MSAModify = GPR[rs]31..0
   elseif cd = 6 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      MSAMap = GPR[rs]31..0
   elseif cd = 7 then
      if not IsCoprocessorEnabled(0) then
         SignalException(CoprocessorUnusableException, 0)
      endif
      MSAUnmap = GPR[rs]31..0
   endif
endif

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception. Coprocessor 0 Unusable

Exception.

Encoding:

Format:

DIV_S.df 

DIV_S.B wd,ws,wt

DIV_S.H wd,ws,wt

DIV_S.W wd,ws,wt

DIV_S.D wd,ws,wt

Purpose:

Vector Signed Divide

Vector signed divide.

Description:

wd[i] = ws[i] div wt[i]

The signed integer elements in vector ws are divided by signed integer elements in vector wt. The result is written to vector wd. If a divisor element vector wt is zero, the result value is UNPREDICTABLE.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

DIV_S.B
   for i in 0 .. WRLEN/8-1
         WR[wd]8i+7..8i = WR[ws]8i+7..8i div WR[wt]8i+7..8i
   endfor
DIV_S.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[ws]16i+15..16i div WR[wt]16i+15..16i
   endfor
DIV_S.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[ws]32i+31..32i div WR[wt]32i+31..32i
   endfor
DIV_S.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[ws]64i+63..64i div WR[wt]64i+63..64i
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

DIV_U.df 

DIV_U.B wd,ws,wt

DIV_U.H wd,ws,wt

DIV_U.W wd,ws,wt

DIV_U.D wd,ws,wt

Purpose:

Vector Unsigned Divide

Vector unsigned divide.

Description:

wd[i] = ws[i] udiv wt[i]

The unsigned integer elements in vector ws are divided by unsigned integer elements in vector wt. The result is written to vector wd. If a divisor element vector wt is zero, the result value is UNPREDICTABLE.

The operands and results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

DIV_U.B
   for i in 0 .. WRLEN/8-1
         WR[wd]8i+7..8i = WR[ws]8i+7..8i udiv WR[wt]8i+7..8i
   endfor
DIV_U.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = WR[ws]16i+15..16i udiv WR[wt]16i+15..16i
   endfor
DIV_U.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = WR[ws]32i+31..32i udiv WR[wt]32i+31..32i
   endfor
DIV_U.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = WR[ws]64i+63..64i udiv WR[wt]64i+63..64i
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

DLSA 

DLSA rd,rs,rt,sa

Purpose:

Doubleword Left Shift Add

To left-shift a doubleword by a fixed number of bits and add the result to another doubleword.

Description:

GPR[rd] = (GPR[rs] << (sa + 1)) + GPR[rt]

The 64-bit doubleword value in GPR rs is shifted left, inserting zeros into the emptied bits; the 64-bit doubleword result is added to the 64-bit value in GPR rt and the 64-bit arithmetic result is placed into GPR rd.

No Integer Overflow exception occurs under any circumstances.

Restrictions:

A Reserved Instruction Exception is signaled if access to 64-bit operations is not enabled or MSA implementation is not present.

Operation:

if Are64bitOperationsEnabled() and Config3MSAP = 1 then
   s = sa + 1
   temp = (GPR[rs](63-s)..0 || 0s) + GPR[rt]
   GPR[rd] = temp63..0
else
   SignalException(ReservedInstruction)
endif

Exceptions:

Reserved Instruction Exception.

Encoding:

Format:

DOTP_S.df 

DOTP_S.H wd,ws,wt

DOTP_S.W wd,ws,wt

DOTP_S.D wd,ws,wt

Purpose:

Vector Signed Dot Product

Vector signed dot product (multiply and then pairwise add the adjacent multiplication results) to double width elements.

Description:

(wd[2i+1], wd[2i]) = signed(ws[2i+1]) * signed(wt[2i+1]) + signed(ws[2i]) * 
signed(wt[2i])

The signed integer elements in vector wt are multiplied by signed integer elements in vector ws producing a result twice the size of the input operands. The multiplication results of adjacent odd/even elements are added and stored to the destination.

The operands are values in integer data format half the size of df. The results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

DOTP_S.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = dotp_s(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 8)
   endfor
DOTP_S.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = dotp_s(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 16)
   endfor
DOTP_S.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = dotp_s(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 32)
   endfor
function mulx_s(ts, tt, n)
   s = (tsn-1)n || tsn-1..0 
   t = (ttn-1)n || ttn-1..0
   p = s * t 
   return p2n-1..0
endfunction mulx_s
function dotp_s(ts, tt, n)
   p1 = mulx_s(ts2n-1..n, tt2n-1..n, n)
   p0 = mulx_s(tsn-1..0, ttn-1..0, n)
   p = p1 + p0
   return p2n-1..0
endfunction dotp_s

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

DOTP_U.df 

DOTP_U.H wd,ws,wt

DOTP_U.W wd,ws,wt

DOTP_U.D wd,ws,wt

Purpose:

Vector Unsigned Dot Product

Vector unsigned dot product (multiply and then pairwise add the adjacent multiplication results) to double width elements.

Description:

(wd[2i+1], wd[2i]) = unsigned(ws[2i+1]) * unsigned(wt[2i+1]) + 
unsigned(ws[2i]) * unsigned(wt[2i])

The unsigned integer elements in v ector wt are multiplied by unsigned integer elements in vector ws producing a result twice the size of the input operands. The multiplication results of adj acent odd/even elements are added and stored to the destination.

The operands are values in integer data format half the size of df. The results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

DOTP_U.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = dotp_u(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 8)
   endfor
DOTP_U.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = dotp_u(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 16)
   endfor
DOTP_U.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = dotp_u(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 32)
   endfor
function mulx_u(ts, tt, n)
   s = 0n || tsn-1..0 
   t = 0n || ttn-1..0
   p = s * t 
   return p2n-1..0
endfunction mulx_s
function dotp_u(ts, tt, n)
   p1 = mulx_u(ts2n-1..n, tt2n-1..n, n)
   p0 = mulx_u(tsn-1..0, ttn-1..0, n)
   p = p1 + p0
   return p2n-1..0
endfunction dotp_u

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

DPADD_S.df 

DPADD_S.H wd,ws,wt

DPADD_S.W wd,ws,wt

DPADD_S.D wd,ws,wt

Purpose:

Vector Signed Dot Product and Add

Vector signed dot p roduct (multiply and then pairwise ad d the adjacent mu ltiplication results) and add to double width elements.

Description:

(wd[2i+1], wd[2i]) = (wd[2i+1], wd[2i]) + signed(ws[2i+1]) * 
signed(wt[2i+1]) + signed(ws[2i]) * signed(wt[2i])

The signed integer elements in vector wt are multiplied by signed integer elements in vector ws producing a result twice the size of the input operands. The multiplication results of adjacent odd/even elements are added to the integer elements in vector wd.

The operands are values in integer data format half the size of df. The results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

DPADD_S.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = 
             WR[wd]16i+15..16i + dotp_s(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 8)
   endfor
DPADD_S.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i =
             WR[wd]32i+31..32i + dotp_s(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 16)
   endfor
DPADD_S.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i =
             WR[wd]64i+63..64i + dotp_s(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 32)
   endfor
function mulx_s(ts, tt, n)
   s = (tsn-1)n || tsn-1..0 
   t = (ttn-1)n || ttn-1..0
   p = s * t 
   return p2n-1..0
endfunction mulx_s
function dotp_s(ts, tt, n)
   p1 = mulx_s(ts2n-1..n, tt2n-1..n, n)
   p0 = mulx_s(tsn-1..0, ttn-1..0, n)
   p = p1 + p0
   return p2n-1..0
endfunction dotp_s

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

DPADD_U.df 

DPADD_U.H wd,ws,wt

DPADD_U.W wd,ws,wt

DPADD_U.D wd,ws,wt

Purpose:

Vector Unsigned Dot Product and Add

Vector unsigned dot product (multiply and then pairwise add the adjacent multiplication results) and add to double width results.

Description:

(wd[2i+1], wd[2i]) = (wd[2i+1], wd[2i]) + unsigned(ws[2i+1]) * 
unsigned(wt[2i+1]) + unsigned(ws[2i]) * unsigned(wt[2i])

The unsigned integer elements in v ector wt are multiplied by unsigned integer elements in vector ws producing a result twice the size of the input operands. The multiplication results of adjacent odd/even elements are added to the integer elements in vector wd.

The operands are values in integer data format half the size of df. The results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

DPADD_U.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = 
             WR[wd]16i+15..16i + dotp_u(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 8)
   endfor
DPADD_U.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i =
             WR[wd]32i+31..32i + dotp_u(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 16)
   endfor
DPADD_U.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i =
             WR[wd]64i+63..64i + dotp_u(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 32)
   endfor
function mulx_u(ts, tt, n)
   s = 0n || tsn-1..0 
   t = 0n || ttn-1..0
   p = s * t 
   return p2n-1..0
endfunction mulx_s
function dotp_u(ts, tt, n)
   p1 = mulx_u(ts2n-1..n, tt2n-1..n, n)
   p0 = mulx_u(tsn-1..0, ttn-1..0, n)
   p = p1 + p0
   return p2n-1..0
endfunction dotp_u

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

DPSUB_S.df 

DPSUB_S.H wd,ws,wt

DPSUB_S.W wd,ws,wt

DPSUB_S.D wd,ws,wt

Purpose:

Vector Signed Dot Product and Subtract

Vector signed dot product (multiply and then pairwise add the adjacent multiplication results) and subtract from double width elements.

Description:

(wd[2i+1], wd[2i]) = (wd[2i+1], wd[2i]) - (signed(ws[2i+1]) * 
signed(wt[2i+1]) + signed(ws[2i]) * signed(wt[2i]))

The signed integer elements in vector wt are multiplied by signed integer elements in vector ws producing a signed result twice the size of the input ope rands. The sum of multiplication results of adjacent odd/even elements is subtracted from the integer elements in vector wd to a signed result.

The operands are values in integer data format half the size of df. The results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

DPSUB_S.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i =
             WR[wd]16i+15..16i - dotp_s(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 8)
   endfor
DPSUB_S.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i =
             WR[wd]32i+31..32i - dotp_s(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 16)
   endfor
DPSUB_S.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i =
             WR[wd]64i+63..64i - dotp_s(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 32)
   endfor
function mulx_s(ts, tt, n)
   s = (tsn-1)n || tsn-1..0 
   t = (ttn-1)n || ttn-1..0
   p = s * t 
   return p2n-1..0
endfunction mulx_s
function dotp_s(ts, tt, n)
   p1 = mulx_s(ts2n-1..n, tt2n-1..n, n)
   p0 = mulx_s(tsn-1..0, ttn-1..0, n)
   p = p1 + p0
   return p2n-1..0
endfunction dotp_s

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

DPSUB_U.df 

DPSUB_U.H wd,ws,wt

DPSUB_U.W wd,ws,wt

DPSUB_U.D wd,ws,wt

Purpose:

Vector Unsigned Dot Product and Subtract

Vector unsigned dot product (multiply and then pairwise add the adjacent multiplication results) and subtract from double width elements.

Description:

(wd[2i+1], wd[2i]) = (wd[2i+1], wd[2i]) - (unsigned(ws[2i+1]) * 
unsigned(wt[2i+1]) + unsigned(ws[2i]) * unsigned(wt[2i]))

The unsigned integer elements in vector wt are multiplied by unsigned integer elements in vector ws producing a positive, unsigned result twice the size of the input operands. The sum of multiplication results of adjacent odd/even elements is subtracted from the integer elements in vector wd to a signed result.

The operands are values in integer data format half the size of df. The results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

DPSUB_U.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = 
             WR[wd]16i+15..16i - dotp_u(WR[ws]16i+15..16i, WR[wt]16i+15..16i, 8)
   endfor
DPSUB_U.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i =
             WR[wd]32i+31..32i - dotp_u(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 16)
   endfor
DPSUB_U.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i =
             WR[wd]64i+63..64i - dotp_u(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 32)
   endfor
function mulx_u(ts, tt, n)
   s = 0n || tsn-1..0 
   t = 0n || ttn-1..0
   p = s * t 
   return p2n-1..0
endfunction mulx_s
function dotp_u(ts, tt, n)
   p1 = mulx_u(ts2n-1..n, tt2n-1..n, n)
   p0 = mulx_u(tsn-1..0, ttn-1..0, n)
   p = p1 + p0
   return p2n-1..0
endfunction dotp_u

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

FADD.df 

FADD.W wd,ws,wt

FADD.D wd,ws,wt

Purpose:

Vector Floating-Point Addition

Vector floating-point addition.

Description:

wd[i] = ws[i] + wt[i]

The floating-point elements in vector wt are added to the floating-point elements in vector ws. The result is written to vector wd.

The add operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The operands and results are values in floating-point data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FADD.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = AddFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
FADD.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = AddFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function AddFP(tt, ts, n)
   /* Implementation defined add operation. */
endfunction AddFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCAF.df 

FCAF.W wd,ws,wt

FCAF.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Always False

Vector to vector floating-point quiet compare always false; all destination bits are clear.

Description:

wd[i] = quietFalse(ws[i], wt[i])

Set all bits to 0 in wd elements. Signaling NaN elements in ws or wt signal Invalid Operation exception.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

0.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FCAF.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = QuietFALSE(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
FCAF.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = QuietFALSE(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function QuietFALSE(tt, ts, n)
   /* Implementation defined signaling NaN test */
   return 0
endfunction QuietFALSE

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCEQ.df 

FCEQ.W wd,ws,wt

FCEQ.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Equal

Vector to vector floating-point quiet compare for equality; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] =(quiet) wt[i])

Set all bits to 1 in wd elements if the corresponding ws and wt floating-point elements are ordered and equal, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

0.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FCEQ.W
   for i in 0 .. WRLEN/32-1
      c = EqualFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = c32
   endfor
FCEQ.D
   for i in 0 .. WRLEN/64-1
      c = EqualFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = c64
   endfor
function EqualFP(tt, ts, n)
   /* Implementation defined quiet equal compare operation. */
endfunction EqualFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCLASS.df 

FCLASS.W wd,ws

FCLASS.D wd,ws

Purpose:

Vector Floating-Point Class Mask

Vector floating-point class shown as a bit mask for Zero, Negative, Infinite, Subnormal, Quiet NaN, or Signaling

NaN.

Description:

wd[i] = class(ws[i])

Store in each element of v ector wd a bit mask reflecting the floating-point class of the correspo nding element of vector ws.

The mask has 10 bits as follows. Bits 0 and 1 indicate NaN values: signaling NaN (bit 0) and quiet NaN (bit 1). Bits

2, 3, 4, 5 classify negative values: infinity (bit 2), normal (bit 3), subnormal (bit 4), and zer o (bit 5). Bits 6, 7, 8, 9 classify positive values:infinity (bit 6), normal (bit 7), subnormal (bit 8), and zero (bit 9).

The input values and generated bit masks are not affected by the flush-to-zero bit FS in MSA Control and Status

Register MSACSR.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

FCLASS.W
   for i in 0 .. WRLEN/32-1
      c = ClassFP(WR[ws]32i+31..32i, 32)
      WR[wd]32i+31..32i = 022 || c9..0
   endfor
FCLASS.D
   for i in 0 .. WRLEN/64-1
      c = ClassFP(WR[ws]64i+63..64i, 64)
      WR[wd]64i+63..64i = 054 || c9..0
   endfor
function ClassFP(tt, n)
   /* Implementation defined class operation. */
endfunction ClassFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

FCLE.df 

FCLE.W wd,ws,wt

FCLE.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Less or Equal

Vector to vector floating-point quiet compare for less than or equal; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] <=(quiet) wt[i])

Set all bits to 1 in wd elements if the corresponding ws floating-point elements are ordered and either less than or equal to wt floating-point elements, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

0.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FCLE.W
   for i in 0 .. WRLEN/32-1
      c = LessFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      d = EqualFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = (c | d)32
   endfor
FCLE.D
   for i in 0 .. WRLEN/64-1
      c = LessFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      d = EqualFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = (c | d)64
   endfor
function LessThanFP(tt, ts, n)
   /* Implementation defined quiet less than compare operation. */
endfunction LessThanFP
function EqualFP(tt, ts, n)
   /* Implementation defined quiet equal compare operation. */
endfunction EqualFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCLT.df 

FCLT.W wd,ws,wt

FCLT.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Less Than

Vector to vector floating-point quiet compare for less than; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] <(quiet) wt[i])

Set all bits to 1 in wd elements if the corresponding ws floating-point elements are ordered and less than wt floatingpoint elements, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

0.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FCLT.W
   for i in 0 .. WRLEN/32-1
      c = LessFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = c32
   endfor
FCLT.D
   for i in 0 .. WRLEN/64-1
      c = LessFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = c64
   endfor
function LessThanFP(tt, ts, n)
   /* Implementation defined quiet less than compare operation. */
endfunction LessThanFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCNE.df 

FCNE.W wd,ws,wt

FCNE.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Not Equal

Vector to vector floating-point quiet compare for not equal; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] !=(quiet) wt[i])

Set all bits to 1 in wd elements if the corresponding ws and wt floating-point elements are ordered and not equal, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

0.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FCNE.W
   for i in 0 .. WRLEN/32-1
      c = NotEqualFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = c32
   endfor
FCNE.D
   for i in 0 .. WRLEN/64-1
      c = NotEqualFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = c64
   endfor
function NotEqualFP(tt, ts, n)
   /* Implementation defined quiet not equal compare operation. */
endfunction NotEqualFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCOR.df 

FCOR.W wd,ws,wt

FCOR.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Ordered

Vector to vector floating-point quiet compare ordered; if true all destination bits are set, otherwise clear.

Description:

wd[i] = ws[i] !?(quiet) wt[i]

Set all bits to 1 in wd elements if the corresponding ws and wt floating-point elements are ordered, i.e. both elements are not NaN values, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

0.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FCOR.W
   for i in 0 .. WRLEN/32-1
      c =OrderedFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = c32
   endfor
FCOR.D
   for i in 0 .. WRLEN/64-1
      c = OrderedFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = c64
   endfor
function OrderedFP(tt, ts, n)
   /* Implementation defined quiet ordered compare operation. */
endfunction OrderedFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCUEQ.df 

FCUEQ.W wd,ws,wt

FCUEQ.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Unordered or Equal

Vector to vector floating-point quiet compare for unordered or equality; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] =?(quiet) wt[i])

Set all bits to 1 in wd elements if the corresponding ws and wt floating-point elements are unordered or equal, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

1.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM

2008.

Operation:

FCUEQ.W
   for i in 0 .. WRLEN/32-1
      c = UnorderedFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      d = EqualFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = (c | d)32
   endfor
FCUEQ.D
   for i in 0 .. WRLEN/64-1
      c = UnorderedFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      d = EqualFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = (c | d)64
   endfor
function UnorderedFP(tt, ts, n)
   /* Implementation defined quiet unordered compare operation. */
endfunction UnorderedFP
function EqualFP(tt, ts, n)
   /* Implementation defined quiet equal compare operation. */
endfunction EqualFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCULE.df 

FCULE.W wd,ws,wt

FCULE.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Unordered or Less or Equal

Vector to vector floating-point quiet compare for unordered or less than or equal; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] <=?(quiet) wt[i])

Set all bits to 1 in wd elements if the corresponding ws floating-point elements are unordered or less than or equal to wt floating-point elements, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

1.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM

2008.

Operation:

FCULE.W
   for i in 0 .. WRLEN/32-1
      c = UnorderedFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      d = LessFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      e = EqualFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = (c | d | e)32
   endfor
FCULE.D
   for i in 0 .. WRLEN/64-1
      c = UnorderedFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      d = LessFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      e = EqualFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = (c | d | e)64
   endfor
function UnorderedFP(tt, ts, n)
   /* Implementation defined quiet unordered compare operation. */
endfunction UnorderedFP
function LessThanFP(tt, ts, n)
   /* Implementation defined quiet less than compare operation. */
endfunction LessThanFP
function EqualFP(tt, ts, n)
   /* Implementation defined quiet equal compare operation. */
endfunction EqualFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCULT.df 

FCULT.W wd,ws,wt

FCULT.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Unordered or Less Than

Vector to vector floating-point quiet compare for unordered or less than; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] <?(quiet) wt[i])

Set all bits to 1 in wd elements if the corresponding ws floating-point elements are unordered or less than wt floatingpoint elements, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

1.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM

2008.

Operation:

FCULT.W
   for i in 0 .. WRLEN/32-1
      c = UnorderedFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      d = LessFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = (c | d)32
   endfor
FCULT.D
   for i in 0 .. WRLEN/64-1
      c = LessFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      d = UnorderedFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = c64
   endfor
function UnorderedFP(tt, ts, n)
   /* Implementation defined quiet unordered compare operation. */
endfunction UnorderedFP
function LessThanFP(tt, ts, n)
   /* Implementation defined quiet less than compare operation. */
endfunction LessThanFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCUN.df 

FCUN.W wd,ws,wt

FCUN.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Unordered

Vector to vector floating-point quiet compare unordered; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] ?(quiet) wt[i])

Set all bits to 1 in wd elements if the corresponding ws and wt floating-point elements are unordered, i.e. at least one element is a NaN value, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

1.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FCUN.W
   for i in 0 .. WRLEN/32-1
      c = UnorderedFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = c32
   endfor
FCUN.D
   for i in 0 .. WRLEN/64-1
      c = UnorderedFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = c64
   endfor
function UnorderedFP(tt, ts, n)
   /* Implementation defined quiet unordered compare operation. */
endfunction UnorderedFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FCUNE.df 

FCUNE.W wd,ws,wt

FCUNE.D wd,ws,wt

Purpose:

Vector Floating-Point Quiet Compare Unordered or Not Equal

Vector to vector floating-point quiet compare for unordered or not equal; if true all destination bits are set, otherwise clear.

Description:

wd[i] = (ws[i] !=?(quiet) wt[i])

Set all bits to 1 in wd elements if the corresponding ws and wt floating-point elements are unordered or not equal, otherwise set all bits to 0.

The quiet compare operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The Inexact Exception is not signaled when subnormal input operands are flushed based on the flush-to-zero bit FS in

MSA Control and Status Register MSACSR. In case of a floating-point exception, the default result has all bits set to

1.

The operands are values in floating-point data format df. The results are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM

2008.

Operation:

FCUNE.W
   for i in 0 .. WRLEN/32-1
      c = UnorderedFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      d = NotEqualFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
      WR[wd]32i+31..32i = (c | d)32
   endfor
FCUNE.D
   for i in 0 .. WRLEN/64-1
      c = UnorderedFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      d = NotEqualFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
      WR[wd]64i+63..64i = (c | d)64
   endfor
function UnorderedFP(tt, ts, n)
   /* Implementation defined quiet unordered compare operation. */
endfunction UnorderedFP
function NotEqualFP(tt, ts, n)
   /* Implementation defined quiet not equal compare operation. */
endfunction NotEqualFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FDIV.df 

FDIV.W wd,ws,wt

FDIV.D wd,ws,wt

Purpose:

Vector Floating-Point Division

Vector floating-point division.

Description:

wd[i] = ws[i] / wt[i]

The floating-point elements in vector ws are divided by the floating-point elements in vector wt. The result is written to vector wd.

The divide operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

The operands and results are values in floating-point data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FDIV.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = DivideFP(WR[ws]32i+31..32i, WR[wt]32i+31..32i, 32)
   endfor
FDIV.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = DivideFP(WR[ws]64i+63..64i, WR[wt]64i+63..64i, 64)
   endfor
function DivideFP(tt, ts, n)
   /* Implementation defined divide operation. */
endfunction DivideFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FEXDO.df 

FEXDO.H wd,ws,wt

FEXDO.W wd,ws,wt

Purpose:

Vector Floating-Point Down-Convert Interchange Format

Vector conversion to smaller interchange format.

Description:

left_half(wd)[i] = down_convert(ws[i]); right_half(wd)[i] = 
down_convert(wt[i])

The floating-point elements in vectors ws and wt are down-converted to a smaller interchange format, i.e. from 64-bit to 32-bit, or from 32-bit to 16-bit.

The format down-conversion operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

16-bit floating-point results are not affected by the flush-to-zero bit FS in MSA Control and Status Register MSACSR.

The operands are values in floating-point data format d ouble the size of df. The results are floating-point values in data format of df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FEXDO.H
   for i in 0 .. WRLEN/32-1
      f = DownConvertFP(WR[ws]32i+31..32i, 32)
      g = DownConvertFP(WR[wt]32i+31..32i, 32)
      WR[wd]16i+15+WRLEN/2..16i+WRLEN/2 = f
      WR[wd]16i+15..16i = g
   endfor
FEXDO.W
   for i in 0 .. WRLEN/64-1
      f = DownConvertFP(WR[ws]64i+63..64i, 64)
      g = DownConvertFP(WR[wt]64i+63..64i, 64)
      WR[wd]32i+31+WRLEN/2..32i+WRLEN/2 = f
      WR[wd]32i+31..32i = g
   endfor
function DownConvertFP(tt, n)
   /* Implementation defined format down-conversion. */
endfunction DownConvertFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FEXP2.df 

FEXP2.W wd,ws,wt

FEXP2.D wd,ws,wt

Purpose:

Vector Floating-Point Base 2 Exponentiation

Vector floating-point base 2 exponentiation.

Description:

wd[i] = ws[i] * 2

wt[i]

The floating-point elements in vector ws are scaled, i.e. multiplied, by 2 to the power of integer elements in vector wt.

The result is written to vector wd.

The operation is the homogeneous scaleB() as defined by the IEEE Standard for Floating-Point Arithmetic 754^TM2008.

The ws operands and wd results are values in floating-point data format df. The wt operands are values in integer data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FEXP2.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = Exp2FP(WR[ws]32i+31..32i, WR[wt]32i+31..32i)
   endfor
FEXP2.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = Exp2FP(WR[ws]64i+63..64i, WR[wt]64i+63..64i)
   endfor
function Exp2FP(tt, ts, n)
   /* Implementation defined tt * 2ts operation. */
endfunction Exp2FP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FEXUPL.df 

FEXUPL.W wd,ws

FEXUPL.D wd,ws

Purpose:

Vector Floating-Point Up-Convert Interchange Format Left

Vector left elements conversion to wider interchange format.

Description:

wd[i] = up_convert(left_half(ws)[i])

The left half floating-point elements in vector ws are up-converted to a larger interchange format, i.e. from 16-bit to

32-bit, or from 32-bit to 64-bit. The result is written to vector wd.

The format up-conversion operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

16-bit floating-point inputs are not affected by the flush-to-zero bit FS in MSA Control and Status Register MSACSR.

The operands are values in floating-point data format half the size of df. The results are floating-point values in data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FEXUPL.W
   for i in 0 .. WRLEN/32-1
      f = UpConvertFP(WR[ws]16i+15+WRLEN/2..16i+WRLEN/2, 16)
      WR[wd]32i+31..32i = f
   endfor
FEXUPL.D
   for i in 0 .. WRLEN/64-1
      f = UpConvertFP(WR[ws]32i+31+WRLEN/2..32i+WRLEN/2, 32)
      WR[wd]64i+63..64i = f
   endfor
function UpConvertFP(tt, n)
   /* Implementation defined format up-conversion. */
endfunction UpConvertFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FEXUPR.df 

FEXUPR.W wd,ws

FEXUPR.D wd,ws

Purpose:

Vector Floating-Point Up-Convert Interchange Format Right

Vector right elements conversion to wider interchange format.

Description:

wd[i] = up_convert(right_half(ws)[i])

The right half floating-point elements in vector ws are up-converted to a larger interchange format, i.e. from 16-bit to

32-bit, or from 32-bit to 64-bit. The result is written to vector wd.

The format up-conversion operation is defined by the IEEE Standard for Floating-Point Arithmetic 754^TM-2008.

16-bit floating-point inputs are not affected by the flush-to-zero bit FS in MSA Control and Status Register MSACSR.

The operands are values in floating-point data format half the size of df. The results are floating-point values in data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FEXUPR.W
   for i in 0 .. WRLEN/32-1
      f = UpConvertFP(WR[ws]16i+15..16i, 16)
      WR[wd]32i+31..32i = f
   endfor
FEXUPR.D
   for i in 0 .. WRLEN/64-1
      f = UpConvertFP(WR[ws]32i+31..32i, 32)
      WR[wd]64i+63..64i = f
   endfor
function UpConvertFP(tt, n)
   /* Implementation defined format up-conversion. */
endfunction UpConvertFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FFINT_S.df 

FFINT_S.W wd,ws

FFINT_S.D wd,ws

Purpose:

Vector Floating-Point Round and Convert from Signed Integer

Vector floating-point round and convert from signed integer.

Description:

wd[i] = from_int_s(ws[i])

The signed integer elements in ws are converted to floating-point values. The result is written to vector wd.

The integer to floating-point conversion operation is defined by the IEEE Standard for Floating-Point Arithmetic

754^TM-2008.

The operands are values in integer data format df. The results are values in floating-point data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FFINT_S.W
   for i in 0 .. WRLEN/32-1
      f = FromIntSignedFP(WR[ws]32i+31..32i, 32)
      WR[wd]32i+31..32i = f
   endfor
FFINT_S.D
   for i in 0 .. WRLEN/64-1
      f = FromIntSignedFP(WR[ws]64i+63..64i, 64)
      WR[wd]64i+63..64i = f
   endfor
function FromFixPointFP(tt, n)
   /* Implementation defined signed integer to floating-point
         conversion. */
endfunction FromFixPointFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FFINT_U.df 

FFINT_U.W wd,ws

FFINT_U.D wd,ws

Purpose:

Vector Floating-Point Convert from Unsigned Integer

Vector floating-point convert from unsigned integer.

Description:

wd[i] = from_int_u(ws[i])

The unsigned integer elements in ws are converted to floating-point values. The result is written to vector wd.

The integer to floating-point conversion operation is defined by the IEEE Standard for Floating-Point Arithmetic

754^TM-2008.

The operands are values in integer data format df. The results are values in floating-point data format df.

Restrictions:

Data-dependent exceptions are poss ible as s pecified by the I EEE Standard for Floating-Point Arithmetic 754^TM2008.

Operation:

FFINT_U.W
   for i in 0 .. WRLEN/32-1
      f = FromIntUnsignedFP(WR[ws]32i+31..32i, 32)
      WR[wd]32i+31..32i = f
   endfor
FFINT_U.D
   for i in 0 .. WRLEN/64-1
      f = FromIntUnsignedFP(WR[ws]64i+63..64i, 64)
      WR[wd]64i+63..64i = f
   endfor
function FromIntUnsignedFP(tt, n)
   /* Implementation defined unsigned integer to floating-point
         conversion. */
endfunction FromIntUnsignedFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception, MSA Floating Point Exception.

Encoding:

Format:

FFQL.df 

FFQL.W wd,ws

FFQL.D wd,ws

Purpose:

Vector Floating-Point Convert from Fixed-Point Left

Vector left fix-point elements format conversion to floating-point doubling the element width.

Description:

wd[i] = from_q(left_half(ws)[i])

The left half fixed-point elements in vector ws are up-converted to floating-point data format, i.e. from 16-bit Q15 to

32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point. The result is written to vector wd.

The fixed-point Q15 or Q31 value is first converted to floating-point as a 16-bit or 32-bit integer (as though it was scaled up by 215 or 231) and then the resulting floating-point value is scaled down (divided by 215 or 231).

The scaling and integer to floating-point conversion operations are defined by the IEEE Standard for Floating-Point

Arithmetic 754^TM-2008. No floating-point exceptions are possible because the input data is half the size of the output.

The operands are values in fixed-point data format half the size of df. The results are floating-point values in data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

FFQL.W
   for i in 0 .. WRLEN/32-1
      f = FromFixPointFP(WR[ws]16i+15+WRLEN/2..16i+WRLEN/2, 16)
      WR[wd]32i+31..32i = f
   endfor
FFQL.D
   for i in 0 .. WRLEN/64-1
      f = FromFixPointFP(WR[ws]32i+31+WRLEN/2..32i+WRLEN/2, 32)
      WR[wd]64i+63..64i = f
   endfor
function FromFixPointFP(tt, n)
   /* Implementation defined fixed-point to floating-point conversion. */
endfunction FromFixPointFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

FFQR.df 

FFQR.W wd,ws

FFQR.D wd,ws

Purpose:

Vector Floating-Point Convert from Fixed-Point Right

Vector right fix-point elements format conversion to floating-point doubling the element width.

Description:

wd[i] = from_q(right_half(ws)[i]);

The right half fixed-point elements in vector ws are up-converted to floating-point data format, i.e. from 16-bit Q15 to

32-bit floating-point, or from 32-bit Q31 to 64-bit floating-point. The result is written to vector wd.

The fixed-point Q15 or Q31 value is first converted to floating-point as a 16-bit or 32-bit integer (as though it was scaled up by 215 or 231) and then the resulting floating-point value is scaled down (divided by 215 or 231).

The scaling and integer to floating-point conversion operations are defined by the IEEE Standard for Floating-Point

Arithmetic 754^TM-2008. No floating-point exceptions are possible because the input data is half the size of the output.

The operands are values in fixed-point data format half the size of df. The results are floating-point values in data format df.

Restrictions:

No data-dependent exceptions are possible.

Operation:

FFQR.W
   for i in 0 .. WRLEN/32-1
      f = FromFixPointFP(WR[ws]16i+15..16i, 16)
      WR[wd]32i+31..32i = f
   endfor
FFQR.D
   for i in 0 .. WRLEN/64-1
      f = FromFixPointFP(WR[wt]32i+31..32i, 32)
      WR[ws]64i+63..64i = f
   endfor
function FromFixPointFP(tt, n)
   /* Implementation defined fixed-point to floating-point conversion. */
endfunction FromFixPointFP

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding:

Format:

FILL.df 

FILL.B wd,rs

FILL.H wd,rs

FILL.W wd,rs

FILL.D wd,rs

Purpose:

Vector Fill from GPR

Vector elements replicated from GPR.

Description:

wd[i] = rs

Replicate GPR rs value to all elements in vector wd. If the source GPR is wider than the destination data format, the destination's elements will be set to the least significant bits of the GPR.

Restrictions:

No data-dependent exceptions are possible.

Operation:

FILL.B
   for i in 0 .. WRLEN/8-1
      WR[wd]8i+7..8i = GPR[rs]7..0
   endfor
FILL.H
   for i in 0 .. WRLEN/16-1
      WR[wd]16i+15..16i = GPR[rs]15..0
   endfor
FILL.W
   for i in 0 .. WRLEN/32-1
      WR[wd]32i+31..32i = GPR[rs]31..0
   endfor
FILL.D
   for i in 0 .. WRLEN/64-1
      WR[wd]64i+63..64i = GPR[rs]63..0
   endfor

Exceptions:

Reserved Instruction Exception, MSA Disabled Exception.

Encoding: