Encoding:

REGIMM

000001

base

ATOMIC

00111

Bit

offset

Format:

ACLR bit, offset(base)

MIPS32, MCU ASE

Atomically Clear Bit within Byte

Purpose:

Atomically Clear Bit within Byte

Description:

Disable interrupts; temp = memory[GPR[base] + offset]; temp = (temp and ~(1<< bit)) ; memory[GPR[base] + offset] = temp; Enable Interrupts

The contents ofthe byte atthe memory location speciied by the effective address are fetched. The speciied bit within the byte is cleared to zero. The modiied byte is stored in memory at the location speciied by the effective address. The 12-bit signed offset is added to the contents of GPR base to form the effective address. The read-modifywrite sequence cannot be interrupted.

Transactions with locking semantics occurin some memory interconnects/busses.Itisimplementation-speciic whether this instruction uses such locking transactions.

Restrictions:

is UNPREDICTABLE if an ACLR instruction is executed in the delay slot of aThe operation ofthe processor branch or jump instruction.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddr_PSIZE-1..2 || (pAddr_1..0 xor ReverseEndian²)
TempIE = Status_IE
Status_IE= 0
memword = LoadMemory (CCA, BYTE, pAddr, vAddr, DATA)
byte = vAddr_1..0xor BigEndianCPU²
temp = memword_{7+8*byte..8*byte}
temp = temp and (( 1 || 0^bit) xor 0xFF))
dataword = temp || 0^8*byte
StoreMemory (CCA, BYTE, dataword, pAddr, vAddr, DATA)
Status_IE= TempIE

Exceptions:

TLB Reill, TLB Invalid, TLB Modiied, Address Error, Watch

Programming Notes:

Upon a TLB miss, a TLBS exception is signalled in the ExcCode ield ofthe Cause register. For address error, a

ADES exception is signalled in the ExcCode ield of the Cause register. For other data-stream related exceptions such as Debug Data Break exceptions and Watch exceptions, it is implementation-speciic whether this instruction is treated as a load or as a store.

Encoding:

REGIMM

000001

base

ATOMIC

00111

Bit

offset

Format:

ASET bit, offset(base)

MIPS32, MCU ASE

Atomically Set Bit within Byte

Purpose:

Atomically Set Bit within Byte

Description:

Disable interrupts;temp = memory[GPR[base] + offset]; temp = (temp or (1 <<bit)) ; memory[GPR[base] + offset] = temp; Enable Interrupts

The contents ofthe byte atthe memory location speciied by the effective address are fetched. The speciied bit within the byte is set to one. The modiied byte is stored in memory at the location speciied by the effective address.

The 12-bit signed offsetis added to the contents of GPR base to form the effective address. The read-modify-write sequence cannot be interrupted.

Transactions with locking semantics occurin some memory interconnects/busses.Itisimplementation-speciic whether this instruction uses such locking transactions.

Restrictions:

is UNPREDICTABLE if an ASET instruction is executed in the delay slot of aThe operation ofthe processor branch or jump instruction.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, STORE)
pAddr = pAddr_PSIZE-1..2 || (pAddr_1..0 xor ReverseEndian²)
TempIE = Status_IE
Status_IE= 0
memword = LoadMemory (CCA, BYTE, pAddr, vAddr, DATA)
byte = vAddr_1..0xor BigEndianCPU²
temp = memword_{7+8*byte..8*byte}
temp = temp or ( 1 || 0^bit)
dataword = temp || 0^8*byte
StoreMemory (CCA, BYTE, dataword, pAddr, vAddr, DATA)
Status_IE= TempIE

Exceptions:

TLB Reill, TLB Invalid, TLB Modiied, Address Error, Watch

Programming Notes:

Upon a TLB miss, a TLBS exception is signalled in the ExcCode ield ofthe Cause register. For address error, a

Encoding:

COP0

010000

00 0000 0000 0000 0000

IRET

111000

Format:

IRET

MIPS32, MCU ASE

Interrupt Return with automated interrupt epilogue handling

Purpose:

Interrupt Return with automated interrupt epilogue handling

Optionally jump directly to another interrupt vector without returning to original return address.

Description:

IRET automates some of the operations that are required when returning from an interrupt handler and can be used in place of the ERET instruction at the end of interrupt handlers. IRET is only appropriate when using Shadow Register

Sets and the EIC Interrupt mode. The automated operations of this instruction can be used to reverse the effects of the automated operations of the Auto-Prologue feature.

If the EIC interrupt mode and the Interrupt Chaining feature are used, the IRET instruction can be used to shorten the time between returning from the current interrupt handler and handling the next requested interrupt.

If the Automated Prologue feature is disabled, then IRET behaves exactly like ERET.

If either the Status_ERL or Status_BEV bits are set, then IRET behaves exactly like ERET.

If Interrupt Chaining is disabled:

Interrupts are disabled. COP0 Status, SRSCtl, and EPC registers are restored from the stack. GPR 29 is incremented for the stack frame size. IRET then clears execution and instruction hazards, conditionally restores

SRSCtl_CSS from SRSCtl_PSS, and returns at the completion of interrupt processing to the interrupted instruction

pointed to by the EPC register.

If Interrupt Chaining is enabled:

Interrupts are disabled. COP0 Status register is restored from the stack. The priority output of the External Interrupt Controller is compared with the IPL ﬁeld of the Status register.

If Status_IPL has a higher priority than or equal to the External Interrupt Controller value:

COP0 SRSCtl and EPC registers are restored from the stack. GPR 29 is incremented for the stack frame size.

IRET then clears execution and instruction hazards, conditionally restores SRSCtl_CSS from SRSCtl_PSS, and returns to the interrupted instruction pointed to by the EPC register at the completion of interrupt processing.

If Status_IPL has a lower priority than the External Interrupt Controller value:

The value of GPR 29 is ﬁrst saved to a temporary register then GPR 29 is incremented for the stack frame size. The EIC is signalled that the next pending interrupt has been accepted. This signalling will update the

Cause_RIPL and SRSCtl_EICSS ﬁelds from the EIC output values. The SRSCtl_EICSS ﬁeld is copied to the

SRSCtl_CSS ﬁeld, while the Cause_RIPL ﬁeld is copied to the Status_IPL ﬁeld. The saved temporary register is

copied to the GPR 29 of the current SRS. The KSU and EXL ﬁelds of the Status register are optionally set to zero. No barrier for execution hazards or instruction hazards is created. IRET ﬁnishes by jumping to the interrupt vector driven by the EIC.

IRET does not execute the next instruction (i.e., it has no delay slot).

Restrictions:

The operation of the processor is UNDEFINED if IRET is executed in the delay slot of a branch or jump instruction.

The operation ofthe processor is UNDEFINED ifIRET is executed when either Shadow Register Sets are not enabled, or when the EIC interrupt mode is not enabled.

An IRET placed between an LL and SC instruction will always cause the SC to fail.

The effective addresses used for stack transactions must be naturally-aligned. If either of the two least-signiﬁcant bits of the address is non-zero, an Address Error exception occurs.

IRET implements a software barrier that resolves all execution and instruction hazards created by Coprocessor 0 state changes

(for Release 2 implementations,referto the SYNCIinstruction for additionalinformation on resolving instruction hazards created by writing the instruction stream). The effects of this barrier begin with the instruction fetch and decode of the instruction at the PC to which the IRET returns.

In a Release 2 implementation, IRET does not restore SRSCtl_CSSfrom SRSCtl_PSSif Status_BEV= 1 or Status_ERL= 1, because any exception that sets StatusERL to 1 (Reset, Soft Reset, NMI, or cache error) does not save SRSCtlCSS in

SRSCtl_PSS. If software sets Status_ERLto 1,it must be aware of the operation of an IRET that may be subsequently executed.

The stack memory transactions behave as individual LW operations with respectto exception reporting. BadVAddr would report the faulting address for an unaligned access, and the faulting word address for unprivileged access, TLB

Reﬁll, and TLB Invalid exceptions. For TLB exceptions, the faulting word address would be reflected in the Context and EntryHi registers. The CacheError register would reflect the faulting word address for Cache Errors.

Operation:

if (( IntCtl_APE == 0) | (Status_ERL== 1) | (Status_BEV== 1))
   Act as ERET // read Operation section of ERET description
else
   temp = 0x4 + GPR[29]
   tempStatus = LoadStackWord(temp)
   ClearHazards()
   if ( (IntCtl_ICE == 0) |  ((IntCtl_ICE == 1) &
   (tempStatus_IPL≥ EIC_{RIPL)) )}
      temp = 0x8 + GPR[29]
      tempSRSCtl = LoadStackWord(temp)
      temp = 0x0 + GPR[29]
      tempEPC = LoadStackWord(temp)
   endif
   Status = tempStatus
   if ( (IntCtl_ICE == 0) | ((IntCtl_ICE == 1) &
      (tempStatus_IPL≥ EIC_{RIPL)) )}
      GPR[29] = GPR[29] + DecodedValue(IntCtl_StkDec)
      SRSCtl_PSS= tempSRSCtl_PSS
      SRSCtl_ESS= tempSRSCtl_ESS
      EPC = tempEPC
      temp = EPC
      Status_EXL= 0
      if (ArchitectureRevision ≥ 2) and (SRSCtl_HSS> 0) and (Status_BEV = 0) then
         SRSCtl_CSS= SRSCtl_PSS
      endif
      if IsMicroMIPSImplemented() then
         PC = temp_31..1 || 0
         ISAMode = temp₀
      else
      endif
      LLbit = 0
      Cause_IC= 0
      ClearHazards()
   else
      Cause_RIPL= EIC_RIPL
      SRSCtl_EICSS= EIC_SS
      temp29 = GPR[29]
      GPR[29] = GPR[29] + DecodedValue(IntCtl_StkDec)
      Status_IPL= Cause_RIPL
      SRSCtl_CSS= SRSCtl_EICSS
      NewShadowSet = SRSCtl_EICSS
      GPR[29] = temp29
      if (IntCtl_ClrEXL== 1)
         Status_EXL= 0
         Status_KSU= 0
      endif
      LLbit = 0
      Cause_IC= 1
      ClearHazards()
      PC = CalcIntrptAddress()
   endif
endif
function LoadStackWord(vaddr)
   if vAddr_1..0!= 0² then
      SignalException(AddressError)
   endif
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
   memword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
   LoadStackWord = memword
endfunction LoadStackWord
function CalcIntrptAddress()
   if StatusBEV == 1
      vectorBase = 0xBFC0.0200
   else
      if ( ArchitectureRevision ≥ 2)
         vectorBase = EBase_31..12|| 0¹¹)
      else
         vectorBase = 0x8000.0000
      endif
   endif
   if (Cause_IV == 0)
      vectorOffset = 0x180
   else
      if (Status_BEV = 1) or (IntCtl_VS = 0)
         vectorOffset = 0x200
      else
         if ( Config3_VEIC == 1 and EIC_Option == 1)
             VectorNum = Cause_RIPL
         elseif (Config3_VEIC == 1 and EIC_Option == 2)
             VectorNum = EIC_VectorNum
         elseif (Config3_VEIC == 0 )
         endif
         if (Config3_VEIC == 1 and EIC_Option == 3)
             vectorOffset = EIC_VectorOffset
         else
             vectorOffset = 0x200 + (VectorNum x (IntCtl_VS|| 0⁵))
         endif
      endif
   endif
   CalcIntrptAddress = vectorBase | vectorOffset
   if (Config3_ISAOnExec)
      CalcIntrptAddress = CalcIntrptAddress_31..1 || 1
   endif
endfunction CalcIntrptAddress

Exceptions:

Coprocessor Unusable Exception, TLB Reﬁll, TLB Invalid, Address Error, Watch, Cache Error, Bus Error

Exceptions