Encoding:

Format:

ABSQ_S.PH  rdt, rts

Purpose:

Find Absolute Value of Two Fractional Halfwords

Find the absolute value of each of a pair of Q15 fractional halfword values with 16-bit saturation.

Description:

rdt = sign_extend(sat16(abs(rts31..16))) || sat16(abs(rts15..0))

For each value in the right-most pair of Q15 fractional halfword values in register rts, the absolute value is found and written to the corresponding Q15 halfword in register rdt. If either input value is the minimum Q15 value (-1.0 in decimal, 0x8000 in hexadecimal), the corresponding result is saturated to 0x7FFF. The upper 32 bits of register rt are ignored.

The sign of the left-most halfword result is extended into the 32 most-significant bits of the destination register.

This instruction sets bit 20 in the DSPControl register in the ouflag field if either input value was saturated.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = satAbs16( GPR[rts]31..16 )
tempA15..0 = satAbs16( GPR[rts]15..0 )
GPR[rdt]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
function satAbs16( a15..0 )
   if ( a15..0 = 0x8000 ) then
      DSPControlouflag:20 = 1
      temp15..0 = 0x7FFF
   else
      if ( a15 = 1 ) then
          temp15..0 = -a15..0
      else
         temp15..0 = a15..0
      endif
   endif
   return temp15..0 
endfunction satAbs16

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ABSQ_S.QB rdt, rts

Purpose:

Find Absolute Value of Four Fractional Byte Values

Find the absolute value of four fractional byte vector elements with saturation.

Description:

rdt = sign_extend(sat8(abs(rts31..24)) || sat8(abs(rts23..16)) || 
sat8(abs(rts15..8)) || sat8(abs(rts7..0)))

For each value in the four right-most Q7 fractional byte elements in register rts, the absolute value is found and written to the corresponding byte in register rdt. If either input value is the minimum Q7 value (-1.0 in decimal, 0x80 in hexadecimal), the corresponding result is saturated to 0x7F. The upper 32 bits of register rts are ignored.

The sign of the left-most byte result is extended into the 32 most-significant bits of destination register rdt.

This instruction sets bit 20 in ouflag field of the DSPControl register if any input value was saturated.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempD7..0 = abs8( GPR[rts]31..24 )
tempC7..0 = abs8( GPR[rts]23..16 )
tempB7..0 = abs8( GPR[rts]15..8 )
tempA7..0 = abs8( GPR[rts]7..0 )
GPR[rdt]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
function abs8( a7..0 )
   if ( a7..0 = 0x80 ) then
      DSPControlouflag:20 = 1
      temp7..0 = 0x7F
   else
      if ( a7 = 1 ) then
          temp7..0 = -a7..0
      else
         temp7..0 = a7..0
      endif
   endif
   return temp7..0 
endfunction abs8

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ABSQ_S.W  rdt, rts

Purpose:

Find Absolute Value of Fractional Word

Find the absolute value of a fractional Q31 value with 32-bit saturation.

Description:

rdt = sign_extend(sat32(abs(rts31..0)))

The absolute value of the right-most Q31 fractional value in register rts is found, sign-extended to 64 bits, and written to destination register rdt. If the input value is the minimum Q31 value (-1.0 in decimal, 0x80000000 in hexadecimal), the result is saturated to 0x7FFFFFFF before being sign-extended and written to register rdt.

This instruction sets bit 20 in the DSPControl register in the ouflag field if the input value was saturated.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

temp31..0 = satAbs32( GPR[rts]31..0 )
GPR[rdt]63..0 = (temp31)32 || temp31..0
function satAbs32( a31..0 )
   if ( a31..0 = 0x80000000 ) then
      DSPControlouflag:20 = 1
      temp31..0 = 0x7FFFFFFF
   else
      if ( a31 = 1 ) then
          temp31..0 = -a31..0
      else
         temp31..0 = a31..0
      endif
   endif
   return temp31..0 
endfunction satAbs32

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ADDQH[_R].PH 

ADDQH.PH     rd, rs, rt

ADDQH_R.PH   rd, rs, rt

Purpose:

Add Fractional Halfword Vectors And Shift Right to Halve Results

Element-wise fractional addition of halfword vectors, with a right shift by one bit to halve each result, with optional rounding.

Description:

rd = sign_extend(round((rs31..16 + rt31..16) >> 1) || round((rs15..0 + rt15..0) >> 1))

Each element from the two right-most halfword values in register rs is added to the corresponding halfword element in register rt to create an interim 17-bit result.

In the non-rounding instruction variant, each interim result is then shifted right by one bit before being written to the corresponding halfword element of destination register rd.

In the rounding version of the instructi on, a value of 1 is added at the least- significant bit position of each interim result; the interim result is then right-shifted by one bit and written to the destination register.

This instruction does not modify the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDQH.PH:
   tempB15..0 = rightShift1AddQ16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = rightShift1AddQ16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
ADDQH_R.PH:
   tempB15..0 = roundRightShift1AddQ16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = roundRightShift1AddQ16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
function rightShift1AddQ16( a15..0 , b15..0 )
   temp16..0 = (( a15 || a15..0 ) + ( b15 || b15..0 ))
   return temp16..1
endfunction rightShift1AddQ16
function roundRightShift1AddQ16( a15..0 , b15..0 )
   temp16..0 = (( a15 || a15..0 ) + ( b15 || b15..0 ))
   temp16..0 = temp16..0 + 1
   return temp16..1
endfunction roundRightShift1AddQ16

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ADDQH[_R].W 

ADDQH.W     rd, rs, rt

ADDQH_R.W   rd, rs, rt

Purpose:

Add Fractional Words And Shift Right to Halve Results

Fractional addition of word vectors, with a right shift by one bit to halve the result, with optional rounding.

Description:

rd = sign_extend(round((rs31..0 + rt31..0) >> 1))

The right-most word in register rs is added to the right-most word in register rt to create an interim 33-bit result.

In the non-rounding instruction variant, the interim result is then shifted right by one bit before being written to the destination register rd.

In the rounding version of the i nstruction, a value of 1 is added at the least-significant bit position of the interim result; the interim result is then right-shifted by one bit and written to the destination register.

This instruction does not modify the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDQH.W:
   tempA31..0 = rightShift1AddQ32( GPR[rs]31..0 , GPR[rt]31..0 )
   GPR[rd]63..0 = (tempB15)32 || tempA31..0
ADDQH_R.W:
   tempA31..0 = roundRightShift1AddQ32( GPR[rs]31..0 , GPR[rt]31..0 )
   GPR[rd]63..0 = (tempB15)32 || tempA31..0
function rightShift1AddQ32( a31..0 , b31..0 )
   temp32..0 = (( a31 || a31..0 ) + ( b31 || b31..0 ))
   return temp32..1
endfunction rightShift1AddQ32
function roundRightShift1AddQ32( a31..0 , b31..0 )
   temp32..0 = (( a31 || a31..0 ) + ( b31 || b31..0 ))
   temp32..0 = temp32..0 + 1
   return temp32..1
endfunction roundRightShift1AddQ32

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ADDQ[_S].PH 

ADDQ.PH   rd, rs, rt

ADDQ_S.PH rd, rs, rt

Purpose:

Add Fractional Halfword Vectors

Element-wise addition of two v ectors of Q15 fractional values to produce a vector of Q15 fractional results, with optional saturation.

Description:

rd = sign_extend(sat16(rs31..16 + rt31..16) || sat16(rs15..0 + rt15..0))

Each of the two right-most fractional halfword elements in register rt are added to the corresponding fractional halfword elements in register rs.

For the non-saturating version of the instruction, the result of each addition is written into the corresponding element in register rd. If the addition results in overflow or underflow, the result modulo 2 is written to the corresponding element in register rd.

For the saturating version of the instruction, signed saturating arithmetic is performed, where an overflow is clamped to the largest representable value (0x7FFF hexadecimal) and an underfl ow to th e smallest representable value

(0x8000 hexadecimal) before being written to the destination register rd.

For each instruction, the sign of the left-most halfword result is extended into the 32 most-significant bits of the destination register.

For each instruction, if either of the individual additions result in underflow, overflow, or saturation, a 1 is written to bit 20 in the DSPControl register in the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDQ.PH:
   tempB15..0 = add16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = add16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
ADDQ_S.PH:
   tempB15..0 = satAdd16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = satAdd16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
function add16( a15..0, b15..0 ) 
   temp16..0 = ( a15 || a15..0 ) + ( b15 || b15..0 )
   if ( temp16 != temp15 ) then
      DSPControlouflag:20 = 1
   endif
   return temp15..0
endfunction add16
function satAdd16( a15..0, b15..0 )
   temp16..0 = ( a15 || a15..0 ) + ( b15 || b15..0 )
   if ( temp16 != temp15 ) then
      if ( temp16 = 0 ) then
          temp15..0 = 0x7FFF
      else
          temp15..0 = 0x8000
      endif
      DSPControlouflag:20 = 1
   endif
   return temp15..0
endfunction satAdd16

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ADDQ_S.W rd, rs, rt

Purpose:

Add Fractional Words

Addition of two Q31 fractional values to produce a Q31 fractional result, with saturation.

Description:

rd = sign_extend(sat32(rs31..0 + rt31..0))

The right-most Q31 fractional word in register rt is added to the corres ponding fractional word in register rs. The result is then sign-extended to 64 bits and written to the destination register rd.

Signed saturating arithmetic is used, where an overflow is clamped to the largest representable value (0x7FFFFFFF hexadecimal) and an underflow to the smallest representable value (0x80000000 hexadecimal) before being signextended and written to the destination register rd.

If the addition results in underflow, overflow, or saturation, a 1 is written to bit 20 in the DSPControl register within the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

temp31..0 = satAdd32( GPR[rs]31..0 , GPR[rt]31..0 )
GPR[rd]63..0 = (temp31)32 || temp31..0
function satAdd32( a31..0, b31..0 )
   temp32..0 = ( a31 || a31..0 ) + ( b31 || b31..0 )
   if ( temp32 != temp31 ) then
      if ( temp32 = 0 ) then
          temp31..0 = 0x7FFFFFFF
      else
          temp31..0 = 0x80000000
      endif
      DSPControlouflag:20 = 1
   endif
   return temp31..0
endfunction satAdd32

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ADDSC rd, rs, rt

Purpose:

Add Signed Word and Set Carry Bit

Add two signed 32-bit values and set the carry bit in the DSPControl register if the addition generates a carry-out bit.

Description:

DSPControl[c],rd = sign_extend(rs + rt)

The right-most 32-bit signed value in register rt is added to the right-most 32-bit signed value in register rs. The result is then sign-extended to 64 bits and written into register rd. The carry bit result out of the addition operation is written to bit 13 (the c field) of the DSPControl register.

This instruction does not modify the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

Operation:

temp32..0 = ( 0 || GPR[rs]31..0 ) + ( 0 || GPR[rt]31..0 )
DSPControlc:13 = temp32 
GPR[rd]63..0 = (temp31)32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

Note that this is really two's complement (modulo) arithmetic on the two integer values, where the overflow is preserved in architectural state. The ADDWC instruction can be used to do an add using this carry bit. These instructions are provided in the MIPS32 ISA to support 64-bit addition and subtraction using two pairs of 3 2-bit GPRs to hold each 64-bit value. In the MIPS64 ISA, 64-bit addition and subtraction can be performed directly, without requiring the use of these instructions.

Encoding:

Format:

ADDUH[_R].QB 

ADDUH.QB     rd, rs, rt

ADDUH_R.QB   rd, rs, rt

Purpose:

Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results

Element-wise unsigned addition of un signed byte vectors, with right shift by one bit to halve each result, with optional rounding.

Description:

rd = round((rs31..24 + rt31..24)>>1) || round((rs23..16 + rt23..16)>>1) ||round((rs15..8 + rt15..8)>>1) || round((rs7..0 + rt7..0)>>1)

Each element from the four unsigned byte values in register rs is added to the corresponding unsigned byte element in register rt to create an unsigned interim result.

In the non-rounding instruction variant, each interim result is then shifted right by one bit before being written to the corresponding unsigned byte element of destination register rd.

In the rounding version of the instructi on, a value of 1 is added at the least- significant bit position of each interim result before being right-shifted by one bit and written to the destination register.

This instruction does not modify the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDUH.QB:
   tempD7..0 = rightShift1AddU8( GPR[rs]31..24 , GPR[rt]31..24 )
   tempC7..0 = rightShift1AddU8( GPR[rs]23..16 , GPR[rt]23..16 )
   tempB7..0 = rightShift1AddU8( GPR[rs]15..8 , GPR[rt]15..8 )
   tempA7..0 = rightShift1AddU8( GPR[rs]7..0 , GPR[rt]7..0 )
   GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
ADDUH_R.QB:
   tempD7..0 = roundRightShift1AddU8( GPR[rs]31..24 , GPR[rt]31..24 )
   tempC7..0 = roundRightShift1AddU8( GPR[rs]23..16 , GPR[rt]23..16 )
   tempB7..0 = roundRightShift1AddU8( GPR[rs]15..8 , GPR[rt]15..8 )
   tempA7..0 = roundRightShift1AddU8( GPR[rs]7..0 , GPR[rt]7..0 )
   GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
function rightShift1AddU8( a7..0 , b7..0 )
   temp8..0 = (( 0 || a7..0 ) + ( 0 || b7..0 ))
   return temp8..1
endfunction rightShift1AddU8
function roundRightShift1AddU8( a7..0 , b7..0 )
   temp8..0 = (( 0 || a7..0 ) + ( 0 || b7..0 ))
   temp8..0 = temp8..0 + 1
   return temp8..1
endfunction roundRightShift1AddU8

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ADDU[_S].PH 

ADDU.PH   rd, rs, rt

ADDU_S.PH rd, rs, rt

Purpose:

Unsigned Add Integer Halfwords

Add two pairs of unsigned integer halfwords, with optional saturation.

Description:

rd = sign_extend(sat16(rs31..16 + rt31..16) || sat16(rs15..0 + rt15..0))

The two right-most unsigned integer halfword elements in register rt are added to the corresponding unsigned integer halfword elements in register rs.

For the non-saturating version of the instruction, the result modulo 65,536 is written into the corresponding element in register rd.

For the saturating version of the instruction, the addition is performed using unsigned saturating arithmetic. Results that overflow are clamped to the largest representable value (65,535 decimal, 0xFFFF hexadecimal) before being written to the destination register rd.

Bit 31 of the result is extended into the 32 most-significant bits of the destination register.

For either instruction, if any of the individual additions result in overflow or saturation, a 1 is written to bit 20 in the

DSPControl register within the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDU.PH:
   tempB15..0 = addU16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = addU16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
ADDU_S.PH:
   tempB15..0 = satAddU16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = satAddU16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ADDU[_S].QB 

ADDU.QB   rd, rs, rt

ADDU_S.QB rd, rs, rt

Purpose:

Unsigned Add Quad Byte Vectors

Element-wise addition of two vectors of unsigned byte values to produce a vector of unsigned byte results, with optional saturation.

Description:

rd = sign_extend(sat8(rs31..24 + rt31..24)) || sat8(rs23..16 + rt23..16) || sat8(rs15..8 + rt15..8) || sat8(rs7..0 + rt7..0)

The four right-most byte elements in register rt are added to the corresponding byte elements in register rs.

For the non-saturating version of the instruction, the result modulo 256 is written into the corresponding element in register rd.

For the saturating version of the instruction, the addition is performed using unsigned saturating arithmetic. Results that overflow are clamped to the largest representable value (255 decimal, 0xFF hexadecimal) before being written to the destination register rd.

Bit 31 of the result is extended into the 32 most-significant bits of the destination register.

For either instruction, if any of the individual additions result in overflow or saturation, a 1 is written to bit 20 in the

DSPControl register within the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDU.QB:
   tempD7..0 = addU8( GPR[rs]31..24 , GPR[rt]31..24 )
   tempC7..0 = addU8( GPR[rs]23..16 , GPR[rt]23..16 )
   tempB7..0 = addU8( GPR[rs]15..8 , GPR[rt]15..8 )
   tempA7..0 = addU8( GPR[rs]7..0 , GPR[rt]7..0 )
   GPR[rd]63..0 = (tempD7)48 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
ADDU_S.QB:
   tempD7..0 = satAddU8( GPR[rs]31..24 , GPR[rt]31..24 )
   tempC7..0 = satAddU8( GPR[rs]23..16 , GPR[rt]23..16 )
   tempB7..0 = satAddU8( GPR[rs]15..8 , GPR[rt]15..8 )
   tempA7..0 = satAddU8( GPR[rs]7..0 , GPR[rt]7..0 )
   GPR[rd]63..0 = (tempD7)48 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
function addU8( a7..0, b7..0 )
   temp8..0 = ( 0 || a7..0 ) + ( 0 || b7..0 )
   if ( temp8 = 1 ) then
      DSPControlouflag:20 = 1
   endif
   return temp7..0
endfunction addU8
function satAddU8( a7..0, b7..0 )
   temp8..0 = ( 0 || a7..0 ) + ( 0 || b7..0 )
   if ( temp8 = 1 ) then
      temp7..0 = 0xFF
      DSPControlouflag:20 = 1
   endif
   return temp7..0
endfunction satAddU8

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

ADDWC rd, rs, rt

Purpose:

Add Word with Carry Bit

Add two signed 32-bit values with the carry bit in the DSPControl register.

Description:

rd = sign_extend(rs + rt + DSPControlc:13)

The right-most 32-bit value in register rt is added to the right-most 32-bit value in register rs and the carry bit in the

DSPControl register. The result is then sign-extended to 64 bits and written to destination register rd.

If the addition results in either overflow or underflow, this instruction writes a 1 t o bit 20 in the ouflag field of the

DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

Operation:

temp32..0 = ( GPR[rs]31 || GPR[rs]31..0 ) + ( GPR[rt]31 || GPR[rt]31..0 ) + ( 032 || DSPControlc:13 )
if ( temp32 != temp31 ) then
   DSPControlouflag:20 = 1
endif
GPR[rd]63..0 = (temp31)32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

APPEND rt, rs, sa

Purpose:

Left Shift and Append Bits to the LSB

Shift a general-purpose register left, inserting bits from the another GPR into the bit positions emptied by the shift.

Description:

rt = sign_extend((rt31..0 << sa4..0) || rssa-1..0

The right-most 32-bit value in register rt is left-shifted by the specified shift amount sa, and sa bits from the least-significant positions of the rs register are inserted into the bit positions in rt emptied by the shift. The 32-bit shifted value is sign-extended to 64 bits and written to destination register rt.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

if ( sa4..0 = 0 ) then 
   temp31..0 = GPR[rt]31..0 
else
   temp31..0 = ( GPR[rt]31-sa..0 || GPR[rs]sa-1..0 )
endif
GPR[rt]63..0 = (temp31)32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

BALIGN rt, rs, bp

Purpose:

Byte Align Contents from Two Registers

Create a word result by combining a specified number of bytes from each of two source registers.

Description:

rt = sign_extend((rt << 8*bp) || (rs >> 8*(4-bp)))

The right-most 32-bit word in register rt is left-shifted as a 32-bit value by bp byte positions, and the right-most word in register rs is right-shifted as a 32-bit value by (4-bp) byte positions. The shifted values are then or-ed together to create a 32-bit result that is sign-extended to 64 bits and written to destination register rt.

The argument bp is provided by the instruction, and is interpreted as an unsigned two-bit integer taking values between zero and three.

Restrictions:

No data-dependent exceptions are possible.

Operation:

if (bp1..0 = 0) or (bp1..0 = 2) then
   GPR[rt]63..0 = UNPREDICTABLE
else 
   temp31..0 = ( GPR[rt]31..0 << (8*bp1..0) ) || ( GPR[rs]31..0 >> (8*(4-bp1..0)) )
   GPR[rt]63..0 = (temp31)32 || temp31..0
endif

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

BITREV rdt, rts

Purpose:

Bit-Reverse Halfword

To reverse the order of the bits of the least-significant halfword in the specified register.

Description:

rdt = zero_extend(rts0..15)

The right-most halfword value in register rts is bit-reversed into the right-most halfword position in the destination register rdt. The 48 most-significant bits of the destination register are zero-filled.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

temp15..0 = GPR[rts]0..15
GPR[rdt]63..0 = 048 || temp15..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

BPOSGE32C offset

Purpose:

Branch on Greater Than or Equal To Value 32 in

DSPControl

Pos Field

Perform a PC-relative branch if the value of the pos field in the DSPControl register is greater than or equal to 32.

Description:

 if (DSPControlpos:6..0 >= 32) then goto PC+offset

First, the offset argument is left-shifted by twoone bits to form an 187-bit signed integer value. This value is added to the address of the instruction immediately following the branch to form a target branch address. Then, if the value of the pos field of the DSPControl register is greater than or equal to 32, the branch is taken and execution begins from the target address.

Restrictions:

If a control transfer instruction (CTI) is executed in the forbidden slot of a branch or jump, Release 6 implementations are required to signal a Reserved Instruction Exception. A CTI is considered to be one of the following instructions: branch, jump, NAL (Release 6), ERET, ERETNC (Release 5), DERET, WAIT, or PAUSE (Release 2). An instruction is in the forbidden slot if it is the instruction following the branch.

Any instruction may be placed at PC + 4, where PC is that of the branch. An exception on such an instruction does not affect CP0 CAUSEBD, and CP0 EPC is that of instruction in slot after branch.

Availability:

This instruction is introduced by and required as of Revision 3 of the DSP Module.

Operation:

I:     se_offsetGPRLEN..0 = ( offset15 )GPRLEN-187 || offset15..0 || 021
      branch_condition = ( DSPControlpos:6..0 >= 32 ? 1 : 0 )
I+1:  if ( branch_condition = 1 ) then
          PCGPRLEN..0 = PCGPRLEN..0 + se_offsetGPRLEN..0
      endif

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

With the 187-bit signed instruction offset, the conditional branch range is ±12864 Kbytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside of this range.

Encoding:

Format:

BPOSGE32 offset

Purpose:

Branch on Greater Than or Equal To Value 32 in

DSPControl

Pos Field

Perform a PC-relative branch if the value of the pos field in the DSPControl register is greater than or equal to 32.

Description:

 if (DSPControlpos:6..0 >= 32) then goto PC+offset

First, the offset argument is left-shifted by twoone bits to form an 187-bit signed integer value. This value is added to the address of the instruction immediately following the branch to form a target branch address. Then, if the value of the pos field of the DSPControl register is greater than or equal to 32, the branch is taken and execution begins from the target address after the instruction in the branch delay slot has been executed.

Restrictions:

Pre-Release 6: Processor operation is UNPREDICTABLE if a control transfer instruction (CTI), specifically a branch, jump, NAL (Release 6), ERET, ERETNC (Release 5), DERET, WAIT, or PAUSE (Release 2) instruction is placed in the delay slot of a branch or jump.

Release 6: If a control transf er instruction (CTI) is executed in the delay slot of a branch o r jump, Release 6 implementations are required to a signal a Reserved Instruction Exception.

Availability:

This instruction has been removed in Release 6.

None.

Operation:

I:     se_offsetGPRLEN..0 = ( offset15 )GPRLEN-187 || offset15..0 || 021
      branch_condition = ( DSPControlpos:6..0 >= 32 ? 1 : 0 )
I+1:  if ( branch_condition = 1 ) then
          PCGPRLEN..0 = PCGPRLEN..0 + se_offsetGPRLEN..0
      endif

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

With the 187-bit signed instruction offset, the conditional branch range is ±12864 Kbytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside of this range.

Encoding:

Format:

CMP.cond.PH 

CMP.EQ.PH  rs, rt

CMP.LT.PH  rs, rt

CMP.LE.PH  rs, rt

Purpose:

Compare Vectors of Signed Integer Halfword Values

Perform an element-wise comparison of two vectors of two signed integer halfwords, recording the results of the comparison in condition code bits.

Description:

DSPControlccond:25..24 = (rs31..16 cond rt31..16) || (rs15..0 cond rt15..0)

The two right-most signed integer halfword elements in register rs are compared with the corresponding signed integer halfword element in register rt. The two 1-bit boolean comparison results are written to bits 24 and 25 of the

DSPControl register’s 8-bit condition code field. The values of the six remaining condition code bits (bits 26 through

31 of the DSPControl register) are UNPREDICTABLE.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

CMP.EQ.PH:
   ccB = GPR[rs]31..16 EQ GPR[rt]31..16 
   ccA = GPR[rs]15..0 EQ GPR[rt]15..0 
   DSPControlccond:25..24 = ccB || ccA
   DSPControlccond:31..26 = UNPREDICTABLE
CMP.LT.PH:
   ccB = GPR[rs]31..16 LT GPR[rt]31..16 
   ccA = GPR[rs]15..0 LT GPR[rt]15..0 
   DSPControlccond:25..24 = ccB || ccA
   DSPControlccond:31..26 = UNPREDICTABLE
CMP.LE.PH:
   ccB = GPR[rs]31..16 LE GPR[rt]31..16 
   ccA = GPR[rs]15..0 LE GPR[rt]15..0 
   DSPControlccond:25..24 = ccB || ccA
   DSPControlccond:31..26 = UNPREDICTABLE

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

CMPGDU.cond.QB 

CMPGDU.EQ.QB  rd, rs, rt

CMPGDU.LT.QB  rd, rs, rt

CMPGDU.LE.QB  rd, rs, rt 

Purpose:

Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl

Compare two vectors of four unsigned bytes each, recording the comparison results in condition code bits that are written to both the specified destination GPR and the condition code bits in the DSPControl register.

Description:

DSPControl[ccond]27..24 = (rs31..24 cond rt31..24) || (rs23..16 cond rt23..16) || (rs15..8 cond rt15..8) || (rs7..0 cond rt7..0);
rd = 0(GPRLEN-4) || DSPControl[ccond]27..24 

Each of the four right-most unsigned byte elements in register rs are compared with the corresponding unsigned byte elements in register rt. The four 1-bit boolean comparison results are written to the four least-significant bits of destination register rd and to bits 24 through 27 of the DSPControl register's 8-bit condition code field. The remaining bits in destination register rd are set to zero. The value of bits 28 through 31 of the DSPControl register's condition code field are UNPREDICTABLE.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

CMPGDU.EQ.QB:
   ccD = GPR[rs]31..24 EQ GPR[rt]31..24 
   ccC = GPR[rs]23..16 EQ GPR[rt]23..16 
   ccB = GPR[rs]15..8 EQ GPR[rt]15..8 
   ccA = GPR[rs]7..0 EQ GPR[rt]7..0 
   DSPControlcc:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
   GPR[rd]63..0 = 0(GPRLEN-4) || ccD || ccC || ccB || ccA
CMPGDU.LT.QB:
   ccD = GPR[rs]31..24 LT GPR[rt]31..24 
   ccC = GPR[rs]23..16 LT GPR[rt]23..16 
   ccB = GPR[rs]15..8 LT GPR[rt]15..8 
   ccA = GPR[rs]7..0 LT GPR[rt]7..0 
   DSPControlcc:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
   GPR[rd]63..0 = 0(GPRLEN-4) || ccD || ccC || ccB || ccA
CMPGDU.LE.QB:
   ccD = GPR[rs]31..24 LE GPR[rt]31..24 
   ccC = GPR[rs]23..16 LE GPR[rt]23..16 
   ccB = GPR[rs]15..8 LE GPR[rt]15..8 
   ccA = GPR[rs]7..0 LE GPR[rt]7..0 
   DSPControlcc:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
   GPR[rd]63..0 = 0(GPRLEN-4) || ccD || ccC || ccB || ccA

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

CMPGU.cond.QB 

CMPGU.EQ.QB  rd, rs, rt

CMPGU.LT.QB  rd, rs, rt

CMPGU.LE.QB  rd, rs, rt

Purpose:

Compare Vectors of Unsigned Byte Values and Write Results to a GPR

Perform an element-wise comparison of two vectors of unsigned bytes, recording the results of the comparison in condition code bits that are written to the specified GPR.

Description:

rd = 060 || (rs31..24 cond rt31..24) || (rs23..16 cond rt23..16) || (rs15..8 cond rt15..8) || (rs7..0 cond rt7..0)

Each of the four right-most unsigned byte elements in register rs are compared with the corresponding unsigned byte elements in register rt. The four 1-bit boolean comparison results are written to the four least-significant bits of destination register rd. The remaining bits in rd are set to zero.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

CMPGU.EQ.QB:
   ccD = GPR[rs]31..24 EQ GPR[rt]31..24 
   ccC = GPR[rs]23..16 EQ GPR[rt]23..16 
   ccB = GPR[rs]15..8 EQ GPR[rt]15..8 
   ccA = GPR[rs]7..0 EQ GPR[rt]7..0 
   GPR[rd]63..0 = 0(GPRLEN-4) || ccD || ccC || ccB || ccA
CMPGU.LT.QB:
   ccD = GPR[rs]31..24 LT GPR[rt]31..24 
   ccC = GPR[rs]23..16 LT GPR[rt]23..16 
   ccB = GPR[rs]15..8 LT GPR[rt]15..8 
   ccA = GPR[rs]7..0 LT GPR[rt]7..0 
   GPR[rd]63..0 = 0(GPRLEN-4) || ccD || ccC || ccB || ccA
CMPGU.LE.QB:
   ccD = GPR[rs]31..24 LE GPR[rt]31..24 
   ccC = GPR[rs]23..16 LE GPR[rt]23..16 
   ccB = GPR[rs]15..8 LE GPR[rt]15..8 
   ccA = GPR[rs]7..0 LE GPR[rt]7..0 
   GPR[rd]63..0 = 0(GPRLEN-4) || ccD || ccC || ccB || ccA

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

CMPU.cond.QB 

CMPU.EQ.QB  rs, rt

CMPU.LT.QB  rs, rt

CMPU.LE.QB  rs, rt

Purpose:

Compare Vectors of Unsigned Byte Values

Perform an element-wise comparison of two vectors of four unsigned bytes, recording the results of the comparison in condition code bits.

Description:

DSPControlccond:27..24 = (rs31..24 cond rt31..24) || (rs23..16 cond rt23..16) || (rs15..8 cond rt15..8) || (rs7..0 cond rt7..0)

Each of the four right-most unsigned byte elements in register rs are compared with the corresponding unsigned byte elements in register rt. The four 1-bit boolean comparison results are written to bits 24 through 27 of the DSPControl register's 8-bit condition code field. The value of bits 28 through 31 of the DSPControl register's condition code field are UNPREDICTABLE.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

CMPU.EQ.QB:
   ccD = GPR[rs]31..24 EQ GPR[rt]31..24 
   ccC = GPR[rs]23..16 EQ GPR[rt]23..16 
   ccB = GPR[rs]15..8 EQ GPR[rt]15..8 
   ccA = GPR[rs]7..0 EQ GPR[rt]7..0 
   DSPControlccond:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
CMPU.LT.QB:
   ccD = GPR[rs]31..24 LT GPR[rt]31..24 
   ccC = GPR[rs]23..16 LT GPR[rt]23..16 
   ccB = GPR[rs]15..8 LT GPR[rt]15..8 
   ccA = GPR[rs]7..0 LT GPR[rt]7..0 
   DSPControlccond:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE
CMPU.LE.QB:
   ccD = GPR[rs]31..24 LE GPR[rt]31..24 
   ccC = GPR[rs]23..16 LE GPR[rt]23..16 
   ccB = GPR[rs]15..8 LE GPR[rt]15..8 
   ccA = GPR[rs]7..0 LE GPR[rt]7..0 
   DSPControlccond:27..24 = ccD || ccC || ccB || ccA
   DSPControlccond:31..28 = UNPREDICTABLE

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPA.W.PH ac, rs, rt

Purpose:

Dot Product with Accumulate on Vector Integer Halfword Elements

Generate the dot-product of two integer halfword vector elements using full-size intermediate products and then accumulate into the specified accumulator register.

Description:

ac = ac + ((rs31..16 * rt31..16) + (rs15..0 * rt15..0))

Each of the two halfword integer values from register rt is multiplied with the corresponding halfword element from register rs to create two integer word results. These two products are summed to generate a dot-product result, which is then accumulated into the specified 64-bit HI/LO accumulator, creating a 64-bit integer result.

The value of ac selects an accumulator numbered from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction does not set any bits of the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = (GPR[rs]31..16 * GPR[rt]31..16)
tempA31..0 = (GPR[rs]15..0 * GPR[rt]15..0)
dotp32..0 = ( tempB31 || tempB31..0 ) + ( tempA31 || tempA31..0 )
acc63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + ( (dotp32)31 || dotp32..0 )
( HI[ac]63..0 || LO[ac]63..0 ) = (acc63)32 || acc63..32 || (acc31)32 || acc31..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPAQX_S.W.PH ac, rs, rt 

Purpose:

Cross Dot Product with Accumulation on Fractional Halfword Elements

Element-wise cross multipli cation of two vectors of fractional halfword elements and accumulation ofthe 32-bit intermediate products into the specified 64-bit accumulator register, with saturation.

Description:

ac = ac + (sat32(rs31..16 * rt15..0) + sat32(rs15..0 * rt31..16))

The left of the right-most Q15 fractional word values from registers rt is multiplied with the right halfword element from register rs and the result left-shifted by one bit position to generate a Q31 fractional format intermediate product. Similarly, the right of the right-most Q15 fractional word values from registers rt is multiplied with the left halfword element from register rs and the result left-shifted by one bit position to generate a Q3 1 fractional format intermediate product. If both multiplicands for either of the multiplications are equal to -1.0 (0x8000 hexadecimal), the resulting intermediate product is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal).

The two intermediate products are then sign-extended and summed to generate a 64-bit, Q32.31 fractional format dotproduct result that is accumulated into the specified 64-bit HI/LO accumulator to produce a final Q32.31 fractional result.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs as a result of a h alfword multiplication, a 1 is written to o ne of bits 1 6 through 19 of the

DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds

to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]15..0 )
tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]31..16 )
dotp63..0 = ( (tempB31)32 || tempB31..0 ) + ( (tempA31)32 || tempA31..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + dotp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0
function multiplyQ15Q15( acc1..0, a15..0, b15..0 )
   if ( a15..0 = 0x8000 ) and ( b15..0 = 0x8000 ) then
      temp31..0 = 0x7FFFFFFF
      DSPControlouflag:16+acc = 1
   else
      temp31..0 = ( a15..0 * b15..0 ) << 1
   endif
   return temp31..0
endfunction multiplyQ15Q15

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPAQX_SA.W.PH ac, rs, rt 

Purpose:

Cross Dot Product with Accumulation on Fractional Halfword Elements

Element-wise cross multipli cation of two vectors of fractional halfword elements and accumulation ofthe 32-bit intermediate products into the specified 64-bit accumulator register, with saturation of the accumulator.

Description:

ac = sat32(ac + (sat32(rs31..16 * rt15..0) + sat32(rs15..0 * rt31..16)))

The left of the right-most Q15 fractional word values from registers rt is multiplied with the right halfword element from register rs and the result left-shifted by one bit position to generate a Q31 fractional format intermediate product. Similarly, the right of the right-most Q15 fractional word values from registers rt is multiplied with the left halfword element from re gister rs and the result left-shifted by one bit position to generate a Q31 fractional format intermediate product. If both multiplicands for either of the multiplications are equal to -1.0 (0x8000 hexadecimal), the resulting intermediate product is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal).

The two intermediate products are then sign-extended and summed to generate a 64-bit, Q32.31 fractional format dotproduct result that is accumulated into the specified 64-bit HI/LO accumulator to produce a Q32.31 fractional result. If this result is larger than or equal to +1.0, or smaller than -1.0, it is saturated to the Q31 range.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs as a result of halfword multiplication or accumulation, a 1 is written to one of bits 16 through 19 of the DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]15..0 )
tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]31..16 )
dotp63..0 = ( (tempB31)32 || tempB31..0 ) + ( (tempA31)32 || tempA31..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + dotp63..0
if ( tempC63 = 0 ) and ( tempC62..31 != 0 ) then
   tempC63..0 = 032 || 0x7FFFFFFF
   DSPControlouflag:16+acc = 1
endif
if ( tempC63 = 1) and ( tempC62..31 != 132) then
   tempC63..0 = 132 || 0x80000000
   DSPControlouflag:16+acc = 1
endif
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0
function multiplyQ15Q15( acc1..0, a15..0, b15..0 )
   if ( a15..0 = 0x8000 ) and ( b15..0 = 0x8000 ) then
      temp31..0 = 0x7FFFFFFF
      DSPControlouflag:16+acc = 1
   else
      temp31..0 = ( a15..0 * b15..0 ) << 1
   endif
   return temp31..0
endfunction multiplyQ15Q15

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPAQ_S.W.PH ac, rs, rt 

Purpose:

Dot Product with Accumulation on Fractional Halfword Elements

Element-wise multiplication of two vectors of fractional halfword elements and accumulation of the accumulated 32bit intermediate products into the specified 64-bit accumulator register, with saturation.

Description:

ac = ac + (sat32(rs31..16 * rt31..16) + sat32(rs15..0 * rt15..0))

Each of the two right-most Q15 fractional word values from registers rt and rs are multiplied together, and the results left-shifted by one bit position to generate two Q31 fractional format intermediate products. If both multiplicands for either of the multiplications are equal to -1.0 (0x8000 hexadecimal), the resulting intermediate product is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal).

The two intermediate products are then sign-extended and summed to generate a 64-bit, Q32.31 fractional format dotproduct result that is accumulated into the specified 64-bit HI/LO accumulator to produce a final Q32.31 fractional result.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs as a result of a h alfword multiplication, a 1 is written to o ne of bits 1 6 through 19 of the

DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds

to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]31..16 )
tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]15..0 )
dotp63..0 = ( (tempB31)32 || tempB31..0 ) + ( (tempA31)32 || tempA31..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + dotp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0
function multiplyQ15Q15( acc1..0, a15..0, b15..0 )
   if ( a15..0 = 0x8000 ) and ( b15..0 = 0x8000 ) then
      temp31..0 = 0x7FFFFFFF
      DSPControlouflag:16+acc = 1
   else
      temp31..0 = ( a15..0 * b15..0 ) << 1
   endif
   return temp31..0
endfunction multiplyQ15Q15

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPAQ_SA.L.W ac, rs, rt 

Purpose:

Dot Product with Accumulate on Fractional Word Element

Multiplication of two fractional word elements, accumulating the product to the specified 64-bit accumulator register, with saturation.

Description:

ac = sat64(ac + sat32(rs31..0 * rt31..0))

The two right-most Q31 fractional word values from registers rt and rs are multiplied together and the result leftshifted by one bit position to generate a 64-bit, Q63 fractional format intermediate product. If both multiplicands are equal to -1.0 (0x80000000 hexadecimal), the intermediate product is saturated to the maximum positive Q63 fractional value (0x7FFFFFFFFFFFFFFF hexadecimal).

The intermediate product is then added to the specified 64-bit HI/LO accumulator, creating a Q63 fractional result. If the accumulation results in overflow or underflow, the accumulator is saturated to either the maximum positive or minimum negative Q63 fractional value (0x8000000000000000 hexadecimal), respectively.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs, a 1 is written to one of bits 16 through 19 of the DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to

ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

dotp63..0 = multiplyQ31Q31( ac, GPR[rs]31..0, GPR[rt]31..0 )
temp64..0 = HI[ac]31 || HI[ac]31..0 || LO[ac]31..0
temp64..0 = temp64..0 + dotp63..0
if ( temp64 != temp63 ) then
   if ( temp64 = 1 ) then
      temp63..0 = 0x8000000000000000
   else
      temp63..0 = 0x7FFFFFFFFFFFFFFF
   endif
   DSPControlouflag:16+ac = 1
endif
( HI[ac]63..0 || LO[ac]63..0 ) = (temp63)32 || temp63..32 || (temp31)32 || temp31..0 
function multiplyQ31Q31( acc1..0, a31..0, b31..0 )
   if (( a31..0 = 0x80000000 ) and ( b31..0 = 0x80000000 )) then
      temp63..0 = 0x7FFFFFFFFFFFFFFF
      DSPControlouflag:16+acc = 1
   else
      temp63..0 = ( a31..0 * b31..0 ) << 1
   endif
   return temp63..0
endfunction multiplyQ31Q31

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPAU.H.QBL ac, rs, rt

Purpose:

Dot Product with Accumulate on Vector Unsigned Byte Elements

Element-wise multiplication of the two left-most elements of the four right-most elements of each of two vectors of unsigned bytes, accumulating the sum of the products into the specified 64-bit accumulator register.

Description:

ac = ac + zero_extend((rs31..24 * rt31..24) + (rs23..16 * rt23..16))

The two left-most elements of the four right-most unsigned byte elements of each of registers rt and rs are multiplied together using unsigned arithmetic to generate two 16-bit unsigned intermediate products. The intermediate products are then zero-extended to 64 bits and accumulated into the specified 64-bit HI/LO accumulator.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction does not set any bits in the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = multiplyU8U8( GPR[rs]31..24, GPR[rt]31..24 )
tempA15..0 = multiplyU8U8( GPR[rs]23..16, GPR[rt]23..16 )
dotp63..0 = ( 048 || tempB15..0 ) + ( 048 || tempA15..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + dotp63..0
( HI[ac]63..0 || LO[ac]63..0 )  = (tempC63)32 || tempC63..32 || (tempC31)32 || 
tempC31..0 
function multiplyU8U8( a7..0, b7..0 )
   temp17..0 = ( 0 || a7..0 ) * ( 0 || b7..0 )
   return temp15..0
endfunction multiplyU8U8

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPAU.H.QBR ac, rs, rt

Purpose:

Dot Product with Accumulate on Vector Unsigned Byte Elements

Element-wise multiplication of the two right-most elements of the four right-most elements of each of two vectors of unsigned bytes, accumulating the sum of the products into the specified 64-bit accumulator register.

Description:

ac = ac + zero_extend((rs15..8 * rt15..8) + (rs7..0 * rt7..0))

The two right-most elements of the four right-most uns igned byte elements of each of registers rt and rs are multiplied together using unsigned arithmetic to generate tw o 16-bit unsigned intermediate products. The intermediate products are then zero-extended to 64 bits and accumulated into the specified 64-bit HI/LO accumulator.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction does not set any bits in the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = multiplyU8U8( GPR[rs]15..8, GPR[rs]15..8 )
tempA15..0 = multiplyU8U8( GPR[rs]7..0, GPR[rs]7..0 )
dotp63..0 = ( 048 || tempB15..0 ) + ( 048 || tempA15..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + dotp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0 

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPAX.W.PH ac, rs, rt

Purpose:

Cross Dot Product with Accumulate on Vector Integer Halfword Elements

Generate the cross dot-product of two integer halfword vector elements using full-size intermediate products and then accumulate into the specified accumulator register.

Description:

ac = ac + ((rs31..16 * rt15..0) + (rs15..0 * rt31..16))

The left halfword integer value from register rt is multiplied with the right halfword element from register rs to create an integer word result. Similarly, the right halfword integer value from register rt is multiplied with the left halfword element from register rs to create the second integer word result. These two products are summed to generate the dotproduct result, which is then accumulated into the specified 64-bit HI/LO accumulator, creating a 64-bit integer result.

The value of ac selects an accumulator numbered from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction will not set any bits of the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = (GPR[rs]31..16 * GPR[rt]15..0)
tempA31..0 = (GPR[rs]15..0 * GPR[rt]31..16)
dotp32..0 = ( (tempB31) || tempB31..0 ) + ( (tempA31) || tempA31..0 )
acc63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + ( (dotp32)31 || dotp32..0 )
( HI[ac]63..0 || LO[ac]63..0 ) = (acc63)32 || acc63..32 || (acc31)32 acc31..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPS.W.PH ac, rs, rt

Purpose:

Dot Product with Subtract on Vector Integer Half-Word Elements

Generate the dot-product of two integer halfword vector elements using full-size intermediate products and then subtract from the specified accumulator register.

Description:

ac = ac - ((rs31..16 * rt31..16) + (rs15..0 * rt15..0))

Each of the two halfword integer values from register rt is multiplied with the corresponding halfword element from register rs to create two integer word results.

These two products are summed to generate the dot-product result, which is then subtracted from the specified 64-bit HI/LO accumulator, creating a 64-bit integer result.

The value of ac selects an accumulator numbered from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction will not set any bits of the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = (GPR[rs]31..16 * GPR[rt]31..16)
tempA31..0 = (GPR[rs]15..0 * GPR[rt]15..0)
dotp32..0 = ( (tempB31) || tempB31..0 ) + ( (tempA31) || tempA31..0 )
acc63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - ( (dotp32)31 || dotp32..0 )
( HI[ac]63..0 || LO[ac]63..0 ) = (acc63)32 || acc63..32 || (acc31)32 || acc31..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPSQX_S.W.PH ac, rs, rt 

Purpose:

Cross Dot Product with Subtraction on Fractional Halfword Elements

Element-wise cross multiplication of two vectors of fractional halfword elements and subtraction of the accumulated

32-bit intermediate products from the specified 64-bit accumulator register, with saturation.

Description:

ac = ac - (sat32(rs31..16 * rt15..0) + sat32(rs15..0 * rt31..16))

The left of the right-most Q15 fractional word values from registers rt is multiplied with the right halfword element from register rs and the result left-shifted by one bit position to generate a Q31 fractional format intermediate product. Similarly, the right of the right-most Q15 fractional word values from registers rt is multiplied with the left halfrs and the result left-shifted by one bit word element from register position to generate a Q3 1 fractional format intermediate product. If both multiplicands for either of the multiplications are equal to -1.0 (0x8000 hexadecimal), the resulting intermediate product is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal).

The two intermediate products are then sign-extended and summed to generate a 64-bit, Q32.31 fractional format dotproduct result that is subtracted from the specified 64-bit HI/LO accumulator to produce a final Q32.31 fractional result.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs as a result of a h alfword multiplication, a 1 is written to o ne of bits 1 6 through 19 of the

DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds

to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]15..0 )
tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]31..16 )
dotp63..0 = ( (tempB31)32 || tempB31..0 ) + ( (tempA31)32 || tempA31..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - dotp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0
function multiplyQ15Q15( acc1..0, a15..0, b15..0 )
   if ( a15..0 = 0x8000 ) and ( b15..0 = 0x8000 ) then
      temp31..0 = 0x7FFFFFFF
      DSPControlouflag:16+acc = 1
   else
      temp31..0 = ( a15..0 * b15..0 ) << 1
   endif
   return temp31..0
endfunction multiplyQ15Q15

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPSQX_SA.W.PH ac, rs, rt 

Purpose:

Cross Dot Product with Subtraction on Fractional Halfword Elements

Element-wise cross multiplication of two vectors of fractional halfword elements and subtraction of the accumulated

32-bit intermediate products from the specified 64-bit accumulator register, with saturation of the accumulator.

Description:

ac = sat32(ac - (sat32(rs31..16 * rt15..0) + sat32(rs15..0 * rt31..16)))

The left of the right-most Q15 fractional word values from registers rt is multiplied with the right halfword element from register rs and the result left-shifted by one bit position to generate a Q31 fractional format intermediate product. Similarly, the right of the right-most Q15 fractional word values from registers rt is multiplied with the left halfrs and the result left-shifted by one bit word element from register position to generate a Q3 1 fractional format intermediate product. If both multiplicands for either of the multiplications are equal to -1.0 (0x8000 hexadecimal), the resulting intermediate product is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal).

The two intermediate products are then sign-extended and summed to generate a 64-bit, Q32.31 fractional format dotproduct result that is subtracted from the specified 64-bit HI/LO accumulator to produce a Q32.31 fractional result. If this result is larger than or equal to +1.0, or smaller than -1.0, it is saturated to the Q31 range.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs as a result of halfword multiplication or accumulation, a 1 is written to one of bits 16 through 19 of the DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]15..0 )
tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]31..16 )
dotp63..0 = ( (tempB31)32 || tempB31..0 ) + ( (tempA31)32 || tempA31..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - dotp63..0
if ( tempC63 = 0 ) and ( tempC62..31 != 0 ) then
   tempC63..0 = 032 || 0x7FFFFFFF
   DSPControlouflag:16+acc = 1
endif
if ( tempC63 = 1) and ( tempC62..31 != 132) then
   tempC63..0 = 132 || 0x80000000
   DSPControlouflag:16+acc = 1
endif
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0
function multiplyQ15Q15( acc1..0, a15..0, b15..0 )
   if ( a15..0 = 0x8000 ) and ( b15..0 = 0x8000 ) then
      temp31..0 = 0x7FFFFFFF
      DSPControlouflag:16+acc = 1
   else
      temp31..0 = ( a15..0 * b15..0 ) << 1
   endif
   return temp31..0
endfunction multiplyQ15Q15

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPSQ_S.W.PH ac, rs, rt 

Purpose:

Dot Product with Subtraction on Fractional Halfword Elements

Element-wise multiplication of two vectors of fractional halfword elements and subtraction of the accumulated 32-bit intermediate products from the specified 64-bit accumulator register, with saturation.

Description:

ac = ac - (sat32(rs31..16 * rt31..16) + sat32(rs15..0 * rt15..0))

Each of the two right-most Q15 fractional word values from registers rt and rs are multiplied together, and the results left-shifted by one bit position to generate two Q31 fractional format intermediate products. If both multiplicands for either of the multiplications are equal to -1.0 (0x8000 hexadecimal), the resulting intermediate product is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal).

The two intermediate products are then sign-extended and summed to generate a 64-bit, Q32.31 fractional format dotproduct result that is subtracted from the specified 64-bit HI/LO accumulator to produce a final Q32.31 fractional result.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs as a result of a h alfword multiplication, a 1 is written to o ne of bits 1 6 through 19 of the

DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds

to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]31..16 )
tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]15..0 )
dotp63..0 = ( (tempB31)32 || tempB31..0 ) + ( (tempA31)32 || tempA31..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - dotp63..0
( HI[ac]63..0 || LO[ac]63..0 )  = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPSQ_SA.L.W ac, rs, rt 

Purpose:

Dot Product with Subtraction on Fractional Word Element

Multiplication of two fractional word elements, subtracting the accumulated product from the specified 64-bit accumulator register, with saturation.

Description:

ac = sat64(ac - sat32(rs31..0 * rt31..0))

The two right-most Q31 fractional word values from registers rt and rs are multiplied together and the result leftshifted by one bit position to generate a 64-bit Q63 fractional format intermediate product. If both multiplicands are equal to -1.0 (0x80000000 hexadecimal), the intermediate product is saturated to the maximum positive Q63 fractional value (0x7FFFFFFFFFFFFFFF hexadecimal).

The intermediate product is then subtracted from the specified 64-bit HI/LO accumulator, creating a Q63 fractional result. If the accumulation results in overflow or underflow, the accumulator is saturated to either the maximum positive or minimum negative Q63 fractional value (0x8000000000000000 hexadecimal), respectively.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs, a 1 is written to one of bits 16 through 19 of the DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to

ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

dotp63..0 = multiplyQ31Q31( ac, GPR[rs]31..0, GPR[rt]31..0 )
temp64..0 = HI[ac]31 || HI[ac]31..0 || LO[ac]31..0
temp64..0 = temp - dotp63..0
if ( temp64 != temp63 ) then
   if ( temp64 = 1 ) then
      temp63..0 = 0x8000000000000000
   else
      temp63..0 = 0x7FFFFFFFFFFFFFFF
   endif
   DSPControlouflag:16+ac = 1
endif
( HI[ac]63..0 || LO[ac]63..0 )  = (temp63)32 || temp63..32 || (temp31)32 || temp31..0 

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPSU.H.QBL ac, rs, rt

Purpose:

Dot Product with Subtraction on Vector Unsigned Byte Elements

Element-wise multiplication of two left-most elements from the four right-most elements of each of two vectors of unsigned bytes, subtracting the sum of the products from the specified 64-bit accumulator register.

Description:

ac = ac - zero_extend((rs31..24 * rt31..24) + (rs23..16 * rt23..16))

The two left-most elements of the four right-most unsigned byte elements of each of registers rt and rs are multiplied together using unsigned arithmetic to generate two 16-bit unsigned intermediate products. The intermediate products are then zero-extended to 64 bits and subtracted from the specified 64-bit HI/LO accumulator. The result of the subtraction is written back to the specified 64-bit HI/LO accumulator.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction does not set any bits in the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = multiplyU8U8( GPR[rs]31..24, GPR[rt]31..24 )
tempA15..0 = multiplyU8U8( GPR[rs]23..16, GPR[rt]23..16 )
dotp63..0 = ( 048 || tempB15..0 ) + ( 048 || tempA15..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - dotp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0 

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPSU.H.QBR ac, rs, rt

Purpose:

Dot Product with Subtraction on Vector Unsigned Byte Elements

Element-wise multiplication of the two right-most elements of the four right-most elements of each of two vectors of unsigned bytes, subtracting the sum of the products from the specified 64-bit accumulator register.

Description:

ac = ac - zero_extend((rs15..8 * rt15..8) + (rs7..0 * rt7..0))

The two right-most elements of the four right-most uns igned byte elements of each of registers rt and rs are multiplied together using unsigned arithmetic to generate tw o 16-bit unsigned intermediate products. The intermediate products are then zero-extended to 64 bits and subtracted from the specified 64-bit HI/LO accumulator.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction does not set any bits in the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = multiplyU8U8( GPR[rs]15..8, GPR[rt]15..8 )
tempA15..0 = multiplyU8U8( GPR[rs]7..0, GPR[rt]7..0 )
dotp63..0 = ( 048 || tempB15..0 ) + ( 048 || tempA15..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - dotp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0 

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

DPSX.W.PH ac, rs, rt

Purpose:

Cross Dot Product with Subtract on Vector Integer Halfword Elements

Generate the cross dot-product of two integer halfword vector elements using full-size intermediate products and then subtract from the specified accumulator register.

Description:

ac = ac - ((rs31..16 * rt15..0) + (rs15..0 * rt31..16))

The left halfword integer value from register rt is multiplied with the right halfword element from register rs to create an integer word result. Similarly, the right halfword integer value from register rt is multiplied with the left halfword element from register rs to create the second integer word result. These two products are summed to generate the dotproduct result, which is then subtracted from the specified 64-bit HI/LO accumulator, creating a 64-bit integer result.

The value of ac selects an accumulator numbered from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction will not set any bits of the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = (GPR[rs]31..16 * GPR[rt]15..0)
tempA31..0 = (GPR[rs]15..0 * GPR[rt]31..16)
dotp32..0 = ( (tempB31) || tempB31..0 ) + ( (tempA31) || tempA31..0 )
acc63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - ( (dotp32)31 || dotp32..0 )
( HI[ac]63..0 || LO[ac]63..0 ) = (acc63)32 || acc63..32 || (acc31)32 acc31..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

EXTPDP rt, ac, size

Purpose:

Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos

Extract size+1 contiguous bits from a 64-bit accumulator from a position specified in the DSPControl register, writing the bits to a GPR with zero-extension and modifying the extraction position.

Description:

rt = zero_extend(acpos..pos-size) ; DSPControlpos:6..0 -= (size+1)

A set of size+1 contiguous bits are extracted from an arbitrary position in accumulator ac, zero-extended to 64 bits, then written to register rt.

The bit position, start_pos, of the first bit of the contiguous set to extract is specified by the pos field in bits 0 through

5 of the DSPControl register; bit 6 of the DSPControl register is ignored. The position of the last bit in the extracted set is start_pos - size, where the size argument is specified in the instruction.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture. After the execution of this instruction, accumulator ac remains unmodified.

If start_possize, the extraction is valid and the value of the pos field in the DSPControl register is decre–(1+)1–>= mented by size+1. Otherwise, the extraction is invalid and is said to have failed. The value of the destination register is UNPREDICTABLE when the extraction is invalid, and the value of the pos field in the DSPControl register (bits

0 through 6) is not modified.

Upon an invalid extraction this instruction writes a 1 to bit 14, the Ex tract Failed Indicator (EFI) bit of the

DSPControl register, and 0 otherwise.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

start_pos5..0 = DSPControlpos:5..0
if ( start_pos - (size+1) >= -1 ) then
   tempsize..0 = ( HI[ac]31..0 || LO[ac]31..0 )start_pos..start_pos-size
   GPR[rt] = 0(GPRLEN-(size+1)) || tempsize..0
   DSPControlpos:6..0 = DSPControlpos:6..0 - (size + 1)
   DSPControlEFI:14 = 0
else
   DSPControlEFI:14 = 1
   GPR[rt] = UNPREDICTABLE
endif

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

EXTPDPV rt, ac, rs

Purpose:

Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos

Extract a fixed number of contiguous bits from a 64-bit accumulator from a position specified in the DSPControl register, writing the bits to a GPR with zero-extension and modifying the extraction position.

Description:

rt = zero_extend(acpos..pos-GPR[rs][4:0]) ; DSPControlpos:6..0 -= (GPR[rs]4..0+1)

ts are extracted from an ar bitrary position in accumulator ac, zero-extended to 64

A fixed number of contiguous bi bits, then written to destination register rt. The number of bits extracted is size+1, where size is specified by the five least-significant bits in register rs, interpreted as a five-bit unsigned integer. The remaining bits in register rs are ignored.

The bit position, start_pos, of the first bit of the contiguous set to extract is specified by the pos field in bits 0 through

5 of the DSPControl register; bit 6 of the DSPControl register is ignored. The position of the last bit in the extracted set is start_pos - size.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture. After the execution of this instruction, accumulator ac remains unmodified.

If start_possize, the extraction is valid and the value of the pos field in the DSPControl register is decre-(1+)1->= mented by size+1. Otherwise, the extraction is invalid and is said to have failed. The value of the destination register is UNPREDICTABLE when the extraction is invalid, and the value of the pos field in the DSPControl register (bits

0 through 6) is not modified.

Upon an invalid extraction this instruction writes a 1 to bit 14, the Ex tract Failed Indicator (EFI) bit of the

DSPControl register, and 0 otherwise.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

start_pos5..0 = DSPControlpos:5..0
size4..0 = GPR[rs]4..0
if ( start_pos - (size+1) >= -1 ) then
   tempsize..0 = ( HI[ac]31..0 || LO[ac]31..0 )start_pos..start_pos-size
   GPR[rt] = 0(GPRLEN-(size+1)) || tempsize..0
   DSPControlpos:6..0 = DSPControlpos:6..0 - (size + 1)
   DSPControlEFI:14 = 0
else
   DSPControlEFI:14 = 1
   GPR[rt] = UNPREDICTABLE
endif

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

EXTP rt, ac, size

Purpose:

Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR

Extract size+1 contiguous bits from a 64-bit accumulator from a position specified in the DSPControl register, writing the bits to a GPR with zero-extension.

Description:

rt = sign_extend(zero_extend(acpos..pos-size))

A set of size+1 contiguous bits are extracted from an arbitrary position in accumulator ac, zero-extended to 64 bits, and then written to register rt.

The bit position, start_pos, of the first bit of the contiguous set to extract is specified by the pos field in bits 0 through

5 of the DSPControl register; bit 6 of the DSPControl register is ignored. The last bit in the set is start_pos - size, where size is specified in the instruction.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture. After the execution of this instruction, accumulator ac remains unmodified.

If start_possize, the extraction is valid, otherwise the extraction is invalid and is said to have failed. The-(1+)1->= value of the destination register is UNPREDICTABLE when the extraction is invalid. Upon an invalid extraction this instruction writes a 1 to bit 14, the Extract Failed Indicator (EFI) bit of the DSPControl register, and 0 otherwise.

Bit 31 of the result is extended into the 32 most-significant bits of the destination register.

The values of bits 0 to 6 in the pos field of the DSPControl register are unchanged by this instruction.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

start_pos5..0 = DSPControlpos:5..0
if ( start_pos - (size+1) >= -1 ) then
   tempsize..0 = ( HI[ac]31..0 || LO[ac]31..0 )start_pos..start_pos-size
   temp31..0 = 0(32-(size+1)) || tempsize..0
   GPR[rt]63..0 = (temp31)32 || temp31..0
   DSPControlEFI:14 = 0
else
   DSPControlEFI:14 = 1
   GPR[rt] = UNPREDICTABLE
endif

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

EXTPV rt, ac, rs

Purpose:

Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR

Extract a variable number of contiguous bits from a 64-bit accumulator from a position specified in the DSPControl register, writing the bits to a GPR with zero-extension.

Description:

rt = zero_extend(acpos..pos-rs[4:0])

A variable number of contiguous bits are extracted from an arbitrary position in accumulator ac, zero-extended to 64 bits, then written to register rt. The number of bits extracted is size+1, where size is specified by the five least-significant bits in register rs, interpreted as a five-bit unsigned integer. The remaining bits in register rs are ignored.

The position of the first bit of the contiguous set to extract, start_pos, is specified by the pos field in bits 0 through 6 of the DSPControl register. The position of the last bit in the contiguous set is start_pos - size.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture. After the execution of this instruction, accumulator ac remains unmodified.

An extraction is valid if start_possize; otherwise, the extraction is invalid and is said to have failed. The-(1+)1->= value of the destination register is UNPREDICTABLE when the extraction is invalid. Upon an invalid extraction this instruction writes a 1 to bit 14, the Extract Failed Indicator (EFI) bit of the DSPControl register, and 0 otherwise.

The values of bits 0 to 6 in the pos field of the DSPControl register are unchanged by this instruction.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

start_pos5..0 = DSPControlpos:5..0
size4..0 = GPR[rs]4..0
if ( start_pos - (size+1) >= -1 ) then
   tempsize..0 = ( HI[ac]31..0 || LO[ac]31..0 )start_pos..start_pos-size
   GPR[rt] = 0(GPRLEN-(size+1)) || tempsize..0
   DSPControlEFI:14 = 0
else
   DSPControlEFI:14 = 1
   GPR[rt] = UNPREDICTABLE
endif

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

EXTRV[_RS].W 

EXTRV.W   rt, ac, rs

EXTRV_R.W rt, ac, rs

EXTRV_RS.W rt, ac, rs

Purpose:

Extract Word Value With Variable Right Shift From Accumulator to GPR

Extract a word value from a 64-bit accumulator to a GPR with varia ble right shift, and with optional rounding or rounding and saturation.

Description:

rt = sign_extend(sat32(round(ac >> rs5..0)))

The value in accumulator ac is shifted right by shift bits with sign extension (arithmetic shift right). The lower 32 bits of the shifted value are then sign extended to 64-bits and written to the destination register rt. The number of bits to shift is given by the five least-significant bits of register rs; the remaining bits of rs are ignored.

The rounding variant of the instruction adds a 1 at the most-significant discarded bit position. The 32 least-significant bits of the rounded result are then sign extended to 64-bits and written to the destination register.

The rounding and saturating variant of the instruction adds a 1 at the most-significant discarded bit position. If the rounding operation results in an overflow, the shifted value is clamped to the maximum positive Q31 fractional value

(0x7FFFFFFF hexadecimal). The rounded and saturated result is then sign extended to 64-bits and written to the destination register.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture. After the execution of this instruction, ac remains unmodified.

For all variants of the instruction, including EXTRV.W, bit 23 of the DSPControl register is set to 1 if eit her of the rounded or non-rounded calculation results in overflow or saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

EXTRV.W:
   temp64..0 = _shiftShortAccRightArithmetic( ac, GPR[rst]4..0 )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   GPR[rt]63..0 = (temp32)32 || temp32..1
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
EXTRV_R.W:
   temp64..0 = _shiftShortAccRightArithmetic( ac, GPR[rst]4..0 )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   GPR[rt]63..0 = (temp32)32 || temp32..1
EXTRV_RS.W:
   temp64..0 = _shiftShortAccRightArithmetic( ac, GPR[rst]4..0 )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      if ( temp64 = 0 ) then
          temp32..1 = 0x7FFFFFFF
      else
          temp32..1 = 0x80000000
      endif
      DSPControlouflag:23 = 1
   endif
   GPR[rt]63..0 = (temp32)32 || temp32..1

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

EXTRV_S.H rt, ac, rs

Purpose:

Extract Halfword Value Variable From Accumulator to GPR With Right Shift and Saturate

Extract a halfword value from a 64-bit accumulator to a GPR with right shift and saturation.

Description:

rt = sign_extend(sat16(ac >> rs4..0))

The value in the 64-bit accumulator ac is shifted right by shift bits with sign extension (arithmetic shift right). The 64bit value is then saturated to 16-bits and sign-extended to 64 bits before being written to the destination register rt.

The five least-significant bits of register rs provide the shift argument, interpreted as a five-bit unsigned integer; the remaining bits in rs are ignored.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture. After the execution of this instruction, ac remains unmodified.

This instruction sets bit 23 of the DSPControl register in the ouflag field if the operation results in saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

shift4..0 = GPR[rs]4..0
temp31..0 = shiftShortAccRightArithmetic( ac, shift )
if ( temp63..0 > 0x0000000000007FFF ) then
   temp31..0 = 0x00007FFF
   DSPControl23 = 1
else if ( temp63..0 < 0xFFFFFFFFFFFF8000 ) then
   temp31..0 = 0xFFFF8000
   DSPControl23 = 1
endif
GPR[rt]63..0 = (temp31)32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

EXTR[_RS].W 

EXTR.W   rt, ac, shift

EXTR_R.W  rt, ac, shift

EXTR_RS.W rt, ac, shift

Purpose:

Extract Word Value With Right Shift From Accumulator to GPR

Extract a word value from a 64-bit accumulator to a GPR with right shift, and with optional rounding or rounding and saturation.

Description:

rt = sign_extend(sat32(round(ac >> shift)))

The value in accumulator ac is shifted right by shift bits with sign extension (arithmetic shift right). The 32 least-significant bits of the shifted value are then sign extended to 64 bits and written to the destination register rts.

The rounding variant of the instruction adds a 1 at the most-significant discarded bit position. The 32 least-significant bits of the rounded result are then sign-extended to 64 bits and written to the destination register.

The rounding and saturating variant of the instruction adds a 1 at the most-significant discarded bit position. If the rounding operation results in an overflow, the shifted value is clamped to the maximum positive Q31 fractional value

(0x7FFFFFFF hexadecimal). The rounded and saturated result is then sign-extended to 64 bits and written to the destination register.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture. After the execution of this instruction, ac remains unmodified.

For all variants of the instruction, including EXTR.W, bit 23 of the DSPControl register is set to 1 if either of the rounded or non-rounded calculation results in overflow or saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

EXTR.W:
   temp64..0 = _shiftShortAccRightArithmetic( ac, shift )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF ) ) then
      DSPControlouflag:23 = 1
   endif
   GPR[rt]63..0 = (temp32)32 || temp32..1
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
EXTR_R.W:
   temp64..0 = _shiftShortAccRightArithmetic( ac, shift )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   GPR[rt]63..0 = (temp32)32 || temp32..1
EXTR_RS.W:
   temp64..0 = _shiftShortAccRightArithmetic( ac, shift )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      if ( temp64 = 0 ) then
          temp32..1 = 0x7FFFFFFF
      else
          temp32..1 = 0x80000000
      endif
      DSPControlouflag:23 = 1
   endif
   GPR[rt]63..0 = (temp32)32 || temp32..1
function _shiftShortAccRightArithmetic( ac1..0, shift4..0 )
   if ( shift4..0 = 0 ) then
      temp64..0 = ( HI[ac]31..0 || LO[ac]31..0 || 0 )
   else
      temp64..0 = ( (HI[ac]31)shift || HI[ac]31..0 || LO[ac]31..shift-1 )
   endif
   return temp64..0
endfunction _shiftShortAccRightArithmetic

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

EXTR_S.H rt, ac, shift

Purpose:

Extract Halfword Value From Accumulator to GPR With Right Shift and Saturate

Extract a halfword value from a 64-bit accumulator to a GPR with right shift and saturation.

Description:

rt = sign_extend(sat16(ac >> shift))

The value in the 64-bit accumulator ac is shifted right by shift bits with sign extension (arithmetic shift right). The 64bit value is then saturated to 16-bits, sign extended to 64 bits, and written to the destination register rt. The shift argument is provided in the instruction.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture. After the execution of this instruction, ac remains unmodified.

This instruction sets bit 23 of the DSPControl register in the ouflag field if the operation results in saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

temp63..0 = shiftShortAccRightArithmetic( ac, shift )
if ( temp63..0 > 0x0000000000007FFF ) then
   temp31..0 = 0x00007FFF
   DSPControlouflag:23 = 1
else if ( temp63..0 < 0xFFFFFFFFFFFF8000 ) then
   temp31..0 = 0xFFFF8000
   DSPControlouflag:23 = 1
endif
GPR[rt]63..0 = (temp31)32 || temp31..0
function shiftShortAccRightArithmetic( ac1..0, shift4..0 )
   sign = HI[ac]31
   if ( shift = 0 ) then
      temp63..0 = HI[ac]31..0 || LO[ac]31..0
   else
      temp63..0 = signshift || (( HI[ac]31..0 || LO[ac]31..0 ) >> shift )
   endif
   if ( sign != temp31 ) then
      DSPControlouflag:23 = 1
   endif
   return temp63..0
endfunction shiftShortAccRightArithmetic

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

INS rt, rs

Restrictions:

The operation is UNPREDICTABLE if lsb > msb.

If either register rs or register rt does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE.

Operation:

if (lsb > msb) or (NotWordValue(GPR[rs])) or (NotWordValue(GPR[rt]))) then
   UNPREDICTABLE
endif
GPR[rt]63..0 = (GPR[rt]31)32 || GPR[rt]31..msb+1 || GPR[rs]msb-lsb..0 || GPR[rt]lsb-1..0

Exceptions:

Reserved Instruction, DSP Disabled

Encoding:

Format:

LBUX rd, index(base)

Purpose:

Load Unsigned Byte Indexed

To load a byte from memory as an unsigned value, using indexed addressing.

Description:

 rd = memory[base+index]

The contents of GPR index is added to the contents of GPR base to form an effective address. The contents of the 8bit byte at the memory location specified by the aligned effective address are fetched, zero-extended to the GPR register length and placed in GPR rd.

Restrictions:

None.

Operation:

vAddr31..0 = GPR[index]31..0 + GPR[base]31..0
( pAddr, CCA ) = AddressTranslation( vAddr, DATA, LOAD )
pAddr = pAddrPSIZE-1..2 || ( pAddr1..0 xor ReverseEndian2 )
memwordGPRLEN..0 = LoadMemory ( CCA, BYTE, pAddr, vAddr, DATA )
GPR[rd]63..0 = zero_extend( memword7..0 )

Exceptions:

Reserved Instruction, DSP Disabled, TLB Refill, TLB Invalid, Bus Error, Address Error, Watch

Encoding:

Format:

LDX rd, index(base)

Purpose:

Load Doubleword Indexed

To load a doubleword value from memory as a signed value, using indexed addressing.

Description:

 rd = memory[base+index]

The contents of GPR index is added to the contents of GPR base to form an effective address. The contents of the 64bit word at the memory location specified by the aligned effective address are fetched and placed in GPR rd.

Restrictions:

The effective address must be naturally-aligned. If any of the three least-significant bits of the address are non-zero, an Address Error exception occurs.

Operation:

vAddr63..0 = GPR[index] + GPR[base]
if ( vAddr2..0 != 03 ) then
   SignalException( AddressError )
endif
( pAddr, CCA ) = AddressTranslation( vAddr, DATA, LOAD )
doubleword63..0 = LoadMemory ( CCA, DOUBLEWORD, pAddr, vAddr, DATA )
GPR[rd]63..0 = doubleword63..0

Exceptions:

Reserved Instruction, DSP Disabled, TLB Refill, TLB Invalid, Bus Error, Address Error, Watch

Encoding:

Format:

LHX rd, index(base)

Purpose:

Load Halfword Indexed

To load a halfword value from memory as a signed value, using indexed addressing.

Description:

 rd = memory[base+index]

The contents of GPR index is added to the contents of GPR base to form an effective address. The contents of the 16bit halfword at the memory location specified by the aligned effective address are fetched, sign-extended to the length of the destination GPR, and placed in GPR rd.

Restrictions:

The effective address must be naturally-aligned. If the l east-significant bit of the effective address is non-zero, an

Address Error exception occurs.

Operation:

vAddr31..0 = GPR[index]31..0 + GPR[base]31..0
if ( vAddr0 != 0 ) then
   SignalException( AddressError )
endif
( pAddr, CCA ) = AddressTranslation( vAddr, DATA, LOAD )
halfwordGPRLEN..0 = LoadMemory( CCA, HALFWORD, pAddr, vAddr, DATA )
GPR[rd]63..0 = sign_extend( halfword15..0 )

Exceptions:

Reserved Instruction, DSP Disabled, TLB Refill, TLB Invalid, Bus Error, Address Error, Watch

Encoding:

Format:

LWX rd, index(base)

Purpose:

Load Word Indexed

To load a word value from memory as a signed value, using indexed addressing.

Description:

 rd = memory[base+index]

The contents of GPR index is added to the contents of GPR base to form an effective address. The contents of the 32bit word at the memory location specified by the aligned effective address are fetched, sign-extended to the length of the GPR register, and placed in GPR rd.

Restrictions:

The effective address must be naturally-aligned. If either of the two least-significant bits of the address are non-zero, an Address Error exception occurs.

Operation:

vAddr31..0 = GPR[index]31..0 + GPR[base]31..0
if ( vAddr1..0 != 02 ) then
   SignalException( AddressError )
endif
( pAddr, CCA ) = AddressTranslation( vAddr, DATA, LOAD )
memwordGPRLEN..0 = LoadMemory( CCA, WORD, pAddr, vAddr, DATA )
GPR[rd]63..0 = sign_extend( memword31..0 )

Exceptions:

Reserved Instruction, DSP Disabled, TLB Refill, TLB Invalid, Bus Error, Address Error, Watch

Encoding:

Format:

MADD ac, rs, rt

Purpose:

Multiply Word and Add to Accumulator

To multiply two 32-bit integer words and add the 64-bit result to the specified accumulator.

Description:

 (HI[ac]||LO[ac]) = (HI[ac]||LO[ac]) + (rs31..0 * rt31..0)

The 32-bit signed integer word in register rs is multiplied by the corresponding 32-bit signed integer word in register

rt to produce a 64-bit result. The 64-bit product is added to the specified 64-bit accumulator.

These special registers HI and LO are specified by the value of ac. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture.

In Release 6 of the MIPS Architecture, accumulators are eliminated from MIPS64.

No arithmetic exception occurs under any circumstances.

Restrictions:

If registers rs or rt do not contain sign-extended 32-bit values (i.e., bits 31 through 63 are equal), then the results of the operation are UNPREDICTABLE.

This instruction does not provide the capability of writing directly to a target GPR.

Operation:

if NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then
   UNPREDICTABLE 
endif
temp63..0 = ((GPR[rs]31)32 || GPR[rs]31..0) * ((GPR[rt]31)32 || GPR[rt]31..0)
acc63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + temp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (acc63)32 || acc63..32 || (acc31)32 || acc31..0

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

In some processors the integer multiply operation may proceed asynchronously and allow other CPU instru ctions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an op portunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel.

Programs that require overflow detection must check for it explicitly.

Where the size of the operands are known, software should place the shorter operand in register rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.

Encoding:

Format:

MADDU ac, rs, rt

Purpose:

Multiply Unsigned Word and Add to Accumulator

To multiply two 32-bit unsigned integer words and add the 64-bit result to the specified accumulator.

Description:

 (HI[ac]||LO[ac]) = (HI[ac]||LO[ac]) + (rs31..0 * rt31..0)

The 32-bit unsigned integer word in register rs is multiplied by the corresponding 32-bit unsigned integer word in register rt to produce a 64-bit result. The 64-bit product is added to the specified 64-bit accumulator.

These special registers HI and LO are specified by the value of ac. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture.

In Release 6 of the MIPS Architecture, accumulators are eliminated from MIPS64.

No arithmetic exception occurs under any circumstances.

Restrictions:

If registers rs or rt do not contain sign-extended 32-bit values (i.e., bits 31 through 63 are equal), then the results of the operation are UNPREDICTABLE.

This instruction does not provide the capability of writing directly to a target GPR.

Operation:

if NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then
   UNPREDICTABLE 
endif
temp64..0 = (032 || GPR[rs]31..0 ) * ( 032 || GPR[rt]31..0 )
acc63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + temp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (acc63)32 || acc63..32 || (acc31)32 || acc31..0

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

In some processors the integer multiply operation may proceed asynchronously and allow other CPU instru ctions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an op portunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel.

Programs that require overflow detection must check for it explicitly.

Where the size of the operands are known, software should place the shorter operand in register rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.

Encoding:

Format:

MAQ_S[A].W.PHL 

MAQ_S.W.PHL  ac, rs, rt 

MAQ_SA.W.PHL ac, rs, rt

Purpose:

Multiply with Accumulate Single Vector Fractional Halfword Element

To multiply one pair of elements from two vectors of fractional halfword values using full-sized intermediate products and accumulate the result into the specified 64-bit accumulator, with optional saturating accumulation.

Description:

ac = sat32(ac + sat32(rs31..16 * rt31..16))

The left-most Q15 fractional halfword values from the two right-most paired halfword vectors in each of registers rt and rs are multiplied together, and the product left-shifted by one bit position to generate a Q31 fractional format intermediate result. If both multiplicands are equal to -1.0 in Q15 fractional format (0x8000 hexadecimal), the intermediate result is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal). The intermediate result is then sign-extended and accumulated into accumulator ac to generate a 64-bit Q32.31 fractional format result.

In the saturating accumulation variant of this instruction, if the accumulation of the intermediate product with the accumulator results in a value that cannot be represented as a Q31 fractional format value, the accumulator is saturated to either the maximum positive Q31 fractional format value (0x7FFFFFFF hexadecimal) or the minimum negative Q31 fractional format value (0x80000000), sign-extended to 64 bits.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If overflow or saturation occurs, a 1 is w ritten to one of bits 16 through 19 of the DSPControl register, within the

ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

MAQ_S.W.PHL:
   tempA31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]31..16 )
   tempB63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + ( (tempA31)32 || tempA31..0 )
   ( HI[ac]63..0 || LO[ac]63..0 )  = (tempB63)32 || tempB63..32 || (tempB31)32 || 
tempB31..0
MAQ_SA.W.PHL:
   tempA31..0 = multiplyQ15Q15( ac, GPR[rs]31..16, GPR[rt]31..16 )
   tempA31..0 = sat32AccumulateQ31( ac, temp )
   tempB63..0 = (tempA31)32 || tempA31..0
   ( HI[ac]63..0 || LO[ac]63..0 )  = (tempB63)32 || tempB63..32 || (tempB31)32 || 
tempB31..0
function sat32AccumulateQ31( acc1..0, a31..0 )
   signA = a31
   temp127..0 = HI[acc]63..0 || LO[acc]63..0
   temp127..0 = temp + ( (signA)96 || a31..0 )
   if ( temp32 != temp31 ) then
      if ( temp32 = 0 ) then
          temp31..0 = 0x80000000
      else
          temp31..0 = 0x7FFFFFFF
      endif
      DSPControlouflag:16+acc = 1
   endif
   return temp31..0
endfunction sat32AccumulateQ31

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

The MAQ_SA version of the instruction is useful for compliance with some ITU speech processing codecs that require a 32-bit saturation after every multiply-accumulate operation.

Encoding:

Format:

MAQ_S[A].W.PHR 

MAQ_S.W.PHR  ac, rs, rt 

MAQ_SA.W.PHR ac, rs, rt

Purpose:

Multiply with Accumulate Single Vector Fractional Halfword Element

To multiply one pair of elements from two vectors of fractional halfword values using full-sized intermediate products and accumulate the result into the specified 64-bit accumulator, with optional saturating accumulation.

Description:

ac = sat32(ac + sat32(rs15..0 * rt15..0))

The right-most Q15 fractiona l halfword values from each of the registers rt and rs are multiplied together and the product left-shifted by one bit position to generate a Q31 fractional format intermediate result. If both multiplicands are equal to -1.0 in Q15 fractional format (0x8000 hexadecimal), the intermediate result is saturated to the maximum positive Q31 fractional value (0x7FFFFFFF hexadecimal). The intermediate result is then sign-extended and accumulated into accumulator ac to generate a 64-bit Q32.31 fractional format result.

In the saturating accumulation variant of this instruction, if the accumulation of the intermediate product with the accumulator results in a value that cannot be represented as a Q31 fractional format value, the accumulator is saturated to either the maximum positive Q31 fractional format value (0x7FFFFFFF hexadecimal) or the minimum negative Q31 fractional format value (0x80000000), sign-extended to 64 bits.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If overflow or saturation occurs, a 1 is w ritten to one of bits 16 through 19 of the DSPControl register, within the

ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

MAQ_S.W.PHR:
   tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]15..0 )
   tempB63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + ( (tempA31)32 || tempA31..0 )
   ( HI[ac]63..0 || LO[ac]63..0 )  = (tempB63)32 || tempB63..32 || (tempB31)32 || tempB31..0
MAQ_SA.W.PHR:
   tempA31..0 = multiplyQ15Q15( ac, GPR[rs]15..0, GPR[rt]15..0 )
   tempA31..0 = sat32AccumulateQ31( ac, temp )
   tempB63..0 = (tempA31)32 || tempA31..0
   ( HI[ac]63..0 || LO[ac]63..0 )  = (tempB63)32 || tempB63..32 || (tempB31)32 || tempB31..0