Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

abs Rd

Rd = |Rd|;

d ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

(RES[31:0] == 0)

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

acall disp

LR = PC + 2;
PC = *(ACBA + (ZE(disp8)<<2));

disp ∈ {0, 4, ..., 1020}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

acr Rd

Rd = Rd + C;

d ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

V = RES[31] AND ~Rd[31]

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0) AND Z

C:

C = ~RES[31] AND Rd[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

adc Rd, Rx, Ry

Rd = Rx + Ry + C;

{d, x, y} ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

V = (Rx[31] AND Ry[31] AND ~RES[31]) OR (~Rx[31] AND ~Ry[31] AND RES[31])

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0) AND Z

C:

C = Rx[31] AND Ry[31] OR Rx[31] AND ~RES[31] OR Ry[31] AND ~RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

add Rd, Rs

Rd = Rd + Rs;

{d, s} ∈ {0, 1, …, 15}

Rev1+

2

add Rd, Rx, Ry << sa

Rd = Rx + (Ry<< sa2);

{d, x, y}∈ {0, 1, …, 15}
sa ∈ {0, 1, 2, 3}

Rev1+

Format I: OP1 = Rd, OP2 = Rs

Format II:OP1 = Rx, OP2 = Ry << sa2

Q:

Not affected

V:

V = (OP1[31] AND OP2[31] AND ~RES[31]) OR (~OP1[31] AND ~OP2[31] AND RES[31])

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = OP1[31] AND OP2[31] OR OP1[31] AND ~RES[31] OR OP2[31] AND ~RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

addabs Rd, Rx, Ry

Rd = Rx + |Ry|;

{d, x, y}∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Z = (RES[31:0] == 0)

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

addhh.wRd, Rx:<part>, Ry:<part>

If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]);
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
Rd = operand1 + operand2;

{d, x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}

Rev1+

OP1 = operand1, OP2 = operand2

Q:

Not affected

V:

V = (OP1[31] AND OP2[31] AND ~RES[31]) OR (~OP1[31] AND ~OP2[31] AND RES[31])

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = OP1[31] AND OP2[31] OR OP1[31] AND ~RES[31] OR OP2[31] AND ~RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

add{cond4}Rd, Rx, Ry

if ( cond4)
Rd = Rx + Ry;

{d, x, y} ∈ {0, 1, …, 15}
cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Rev2+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

and Rd, Rs

Rd = Rd AND Rs;

{d, s} ∈ {0, 1, …, 15}

Rev1+

2

and Rd, Rx, Ry << sa

Rd = Rx AND (Ry << sa5);

{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

3

and Rd, Rx, Ry >> sa

Rd = Rx AND (Ry >> sa5);

{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

andh Rd, imm

Rd[31:16] = Rd[31:16] AND imm16;

d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

2

andh Rd, imm, COH

Rd[31:16] = Rd[31:16] AND imm16;
Rd[15:0] = 0;

d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

3

andl Rd, imm

Rd[15:0] = Rd[15:0]   AND imm16;

d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

4

andl Rd, imm, COH

Rd[15:0] = Rd[15:0]   AND imm16;
Rd[31:16] = 0;

d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

andn Rd, Rs

Rd = Rd AND ~Rs;

{d, s} ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

and{cond4}Rd, Rx, Ry

if ( cond4)
Rd = Rx AND Ry;

{d, x, y} ∈ {0, 1, …, 15}
cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Rev2+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

asr Rd, Rx, Ry

Rd = ASR(Rx, Ry[4:0]);

d, x, y ∈ {0, 1, …, 15}

Rev1+

2

asr Rd, sa

Rd = ASR(Rd, sa5); 

d ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

3

asr Rd, Rs, sa

Rd = ASR(Rs, sa5);

{d,s} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

Format I: Shamt = Ry[4:0], Op = Rx

Format II: Shamt = sa5, Op = Rd

Format III: Shamt = sa5, Op = Rs

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

if (Shamt != 0) then

C = Op[Shamt-1]

else

C = 0

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

bfexts Rd, Rs, bp5, w5

Rd = SE(Rs[bp5+w5-1:bp5]);

{d, s} ∈ {0, 1, …, 15}
{bp5, w5} ∈ {0, 1, ..., 31}

Rev1+

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

bfextu Rd, Rs, bp5, w5

Rd = ZE(Rs[bp5+w5-1:bp5]);

{d, s} ∈ {0, 1, …, 15}
{bp5, w5} ∈ {0, 1, ..., 31}

Rev1+

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

bfins Rd, Rs, bp5, w5

Rd[bp5+w5-1:bp5] = Rs[w5-1:0];

{d, s} ∈ {0, 1, …, 15}
{bp5, w5} ∈ {0, 1, ..., 31}

Rev1+

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

bld Rd, bp

C = Rd[bp5];
Z = Rd[bp5];

d ∈{0, 1, …, 15}
bp ∈ {0, 1, …, 31}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Z = Rd[bp5]

C:

C = Rd[bp5]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

breakpoint

if (SR[DM]==0)
     RSR_DBG = SR;
     RAR_DBG = address of first non-completed instruction;
     SR[R] = 1;
     SR[J] = 1;
     SR[D] = 1;
     SR[M2:M0] = B'110;
     SR[DM] = 1;
     SR[EM] = 1;
     SR[GM] = 1;
     PC = EVBA+0x1C;
else
     PC = PC + 2;

None

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

brev Rd

Rd[31:0] = Rd[0:31];

d  ∈{0, 1, …, 15}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Z = (RES[31:0] == 0)

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

br{cond3}disp

if (cond3)
      PC = PC + (SE(disp8) << 1);
else
      PC = PC + 2;

cond3 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl}
disp ∈ {-256, -254, ..., 254}

Rev1+

2

br{cond4}disp

if (cond4)
      PC = PC + (SE(disp21) << 1);
else
      PC = PC + 4;

cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}
disp ∈ {-2097152, -2097150, ..., 2097150}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

bst Rd, bp

Rd[bp5] = C;

d ∈ {0, 1, …, 15}
bp ∈ {0, 1, …, 31}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

cache Rp[disp], Op5

Issue a command to the cache

disp ∈ {-1024, -1023, ..., 1023}
p ∈ {0, 1, …, 15}

Rev1+

Op[4:3]

Semantic

00

Instruction Cache

01

Data Cache or unified cache

10

Secondary Cache

11

Tertiary Cache

Op[2:0]

Semantic

000

Implementation definedk

001

Implementation defined

010

Implementation defined

011

Implementation defined

100

Implementation defined

101

Implementation defined

110

Implementation defined

111

Implementation defined

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

casts.h Rd

Rd[31:16] = Rd[15];

d ∈ {0, 1, …, 15}

Rev1+

2

casts.b Rd

Rd[31:8] = Rd[7];

d ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

castu.h Rd

Rd[31:16] = 0;

d ∈ {0, 1, …, 15}

Rev1+

2

castu.b Rd

Rd[31:8] = 0:

d ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

cbr Rd, bp

Rd[bp5] = 0;

d ∈ {0, 1, …, 15}
bp ∈ {0, 1, …, 31}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Z = (RES[31:0] == 0)

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

clz Rd, Rs

temp = 32;
for (i = 31; i >= 0; i--)
      if (Rs[i] == 1) then
            temp  =  31 - i;
            break;
Rd = temp;

{d, s} ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Z = (RES[31:0] == 0)

C:

C = (RES[31:0] == 32)

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

com Rd

Rd = ~Rd;

d ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Z = (RES[31:0] == 0)

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

cop CP#, CRd, CRx, CRy, Op

CP#(CRd) = CP#(CRx) Op CP#(CRy);

# ∈ {0, 1, …, 7}
Op ∈ {0, 1, …, 127}
{d, x, y} ∈ {0, 1, …, 15}

Rev1+

Q:

Coprocessor-specific

V:

Coprocessor-specific

N:

Coprocessor-specific

Z:

Coprocessor-specific

C:

Coprocessor-specific

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

cp.b Rd, Rs

Rd[7:0] - Rs[7:0];

{d, s} ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

V = (Rd[7] AND ~Rs[7] AND ~RES[7]) OR (~Rd[7] AND Rs[7] AND RES[7])

N:

N = RES[7]

Z:

Z = (RES[7:0] == 0)

C:

C = ~Rd[7] AND Rs[7] OR Rs[7] AND RES[7] OR ~Rd[7] AND RES[7]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

cp.h Rd, Rs

Rd[15:0] - Rs[15:0];

{d, s} ∈ {0, 1, …, 15}

Rev1+

Format I: OP1 = Rd, OP2 = Rs

Q:

Not affected

V:

V = (OP1[15] AND ~OP2[15] AND ~RES[15]) OR (~OP1[15] AND OP2[15] AND RES[15])

N:

N = RES[15]

Z:

Z = (RES[15:0] == 0)

C:

C = ~OP1[15] AND OP2[15] OR OP2[15] AND RES[15] OR ~OP1[15] AND RES[15]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

cp.w Rd, Rs

Rd - Rs;

{d, s} ∈ {0, 1, …, 15}

Rev1+

2

cp.w Rd, imm

Rd - SE(imm6);

d ∈ {0, 1, …, 15}
imm ∈ {-32, -31, ..., 31}

Rev1+

3

cp.w Rd, imm

Rd - SE(imm21);

d ∈ {0, 1, …, 15}
imm ∈ {-1048576, -104875, ..., 1048575}

Rev1+

Format I: OP1 = Rd, OP2 = Rs

Format II: OP1 = Rd, OP2 = SE(imm6)

Format III:OP1 = Rd, OP2 = SE(imm21)

Q:

Not affected

V:

V = (OP1[31] AND ~OP2[31] AND ~RES[31]) OR (~OP1[31] AND OP2[31] AND RES[31])

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = ~OP1[31] AND OP2[31] OR OP2[31] AND RES[31] OR ~OP1[31] AND RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

cpc Rd, Rs

Rd - Rs - C;

{d, s} ∈ {0, 1, …, 15}

Rev1+

2

cpc Rd

Rd - C;

d ∈ {0, 1, …, 15}

Rev1+

In format II, Rs referred to below equals zero.

Q:

Not affected

V:

V = (Rd[31] AND ~Rs[31] AND ~RES[31]) OR (~Rd[31] AND Rs[31] AND RES[31])

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0) AND Z

C:

C = ~Rd[31] AND Rs[31] OR Rs[31] AND RES[31] OR ~Rd[31] AND RES[31]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

csrf bp

SR[bp5] = 0;

bp ∈ {0, 1, …, 31}

Rev1+

SR[bp5] = 0, all other flags unchanged.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

csrfcz bp

C = SR[bp5];
Z = SR[bp5];

bp ∈ {0, 1, …, 31}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Z = SR[bp5]

C:

C = SR[bp5]

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

divs Rd, Rx, Ry

Rd = Rx / Ry;
Rd+1 = Rx % Ry;

d ∈ {0, 2, …, 14}
{x, y} ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

divu Rd, Rx, Ry

Rd = Rx / Ry;
Rd+1 = Rx % Ry;

d ∈ {0, 2, …, 14}
{x, y} ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

eor Rd, Rs

Rd = Rd XOR Rs;

{d, s} ∈ {0, 1, …, 15}

Rev1+

2

eor Rd, Rx, Ry << sa

Rd = Rx XOR (Ry << sa5);

{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

3

eor Rd, Rx, Ry >> sa

Rd = Rx XOR (Ry >> sa5);

{d, x, y} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

eorh Rd, imm

Rd[31:16] = Rd[31:16] XOR imm16

d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

2

eorl Rd, imm

Rd[15:0]   = Rd[15:0] XOR imm16

d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}

Rev1+

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

eor{cond4} Rd, Rx, Ry

if ( cond4)
Rd = Rx XOR Ry;

{d, x, y} ∈ {0, 1, …, 15}
cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Rev2+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

frs

Invalidate all entries in the return address stack.

none

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

icall Rd

LR = PC + 2;
PC = Rd;

d ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

incjosp imm

if ( JOSP[3:0] + imm < 0 ) 
      TRAP 4
else if (JOSP[3:0] + imm > 8 ) 
      TRAP 3
else
      JOSP = JOSP + imm;

imm ∈ {-4, -3, -2, -1, 1, 2, 3, 4}

Rev1+

imm3

imm

100

-4

101

-3

110

-2

111

-1

000

1

001

2

010

3

011

4

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.d Rd, Rp++

Rd+1:Rd = *(Rp);
Rp = Rp + 8;

d ∈ {0, 2, 4, …, 14}
p, b, i ∈ {0, 1, …, 15}

Rev1+

2

ld.d Rd, --Rp

Rp = Rp - 8;
Rd+1:Rd = *(Rp);

d ∈ {0, 2, 4, …, 14}
p, b, i ∈ {0, 1, …, 15}

Rev1+

3

ld.d Rd, Rp

Rd+1:Rd = *(Rp);

d ∈ {0, 2, 4, …, 14}
p, b, i ∈ {0, 1, …, 15}

Rev1+

4

ld.d Rd, Rp[disp]

Rd+1:Rd = *(Rp + (SE(disp16)));

d ∈ {0, 2, 4, …, 14}
p, b, i ∈ {0, 1, …, 15}

Rev1+

5

ld.d Rd, Rb[Ri<<sa]

Rd+1:Rd = *(Rb + (Ri << sa2));

d ∈ {0, 2, 4, …, 14}
p, b, i ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.sb Rd, Rp[disp]

Rd = SE( *(Rp + (SE(disp16))) );

d, p ∈ {0, 1, …, 15}
disp ∈ {-32768, -32767, ..., 32767}

Rev1+

2

ld.sb Rd, Rb[Ri<<sa]

Rd = SE( *(Rb + (Ri << sa2)) );

d, b, i ∈ {0, 1, …, 15}
sa ∈ {0, 1, 2, 3}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.sb{cond4} Rd, Rp[disp]

if (cond4)
Rd = SE( *(Rp + (ZE(disp9))) );

d, p ∈ {0, 1, …, 15}
disp ∈ {0, 1, ..., 511}
cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Rev2+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.sh Rd, Rp++

Rd = SE( *(Rp) );
Rp = Rp + 2;

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

2

ld.sh Rd, --Rp

Rp = Rp - 2;
Rd = SE( *(Rp) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

3

ld.sh Rd, Rp[disp]

Rd = SE( *(Rp + (ZE(disp3) << 1)) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

4

ld.sh Rd, Rp[disp]

Rd = SE( *(Rp + (SE(disp16)));

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

5

ld.sh Rd, Rb[Ri<<sa]

Rd = SE( *(Rb + (Ri << sa2));

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.sh{cond4} Rd, Rp[disp]

if (cond4)
Rd = SE( *(Rp + (ZE(disp9<<1))) );

d, p ∈ {0, 1, …, 15}
disp ∈ {0, 2, ..., 1022}
cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Rev2+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.ub Rd, Rp++

Rd = ZE( *(Rp) );
Rp = Rp + 1;

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

2

ld.ub Rd, --Rp

Rp = Rp - 1;
Rd = ZE( *(Rp) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

3

ld.ub Rd, Rp[disp]

Rd = ZE( *(Rp + (ZE(disp3))) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

4

ld.ub Rd, Rp[disp]

Rd = ZE( *(Rp + (SE(disp16))) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

5

ld.ub Rd, Rb[Ri<<sa]

Rd = ZE( *(Rb + (Ri << sa2)) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.ub{cond4} Rd, Rp[disp]

if (cond4)
Rd = ZE( *(Rp + (ZE(disp9))) );

d, p ∈ {0, 1, …, 15}
disp ∈ {0, 1, ..., 511}
cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Rev2+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.uh Rd, Rp++

Rd = ZE( *(Rp) );
Rp = Rp + 2;

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

2

ld.uh Rd, --Rp

Rp = Rp - 2;
Rd = ZE( *(Rp) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

3

ld.uh Rd, Rp[disp]

Rd = ZE( *(Rp + (ZE(disp3) << 1)) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

4

ld.uh Rd, Rp[disp]

Rd = ZE( *(Rp + (SE(disp16))) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

5

ld.uh Rd, Rb[Ri<<sa]

Rd = ZE( *(Rb + (Ri << sa2)) );

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.uh{cond4} Rd, Rp[disp]

if (cond4)
Rd = ZE( *(Rp + (ZE(disp9<<1))) );

d, p ∈ {0, 1, …, 15}
disp ∈ {0, 2, ..., 1022}
cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Rev2+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.w Rd, Rp++

Rd =  *(Rp);
Rp = Rp + 4;

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

2

ld.w Rd, --Rp

Rp = Rp - 4;
Rd = *(Rp);

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

3

ld.w Rd, Rp[disp]

Rd = *(Rp + (ZE(disp5) << 2));

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

4

ld.w Rd, Rp[disp]

Rd = *(Rp + (SE(disp16)));

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

5

ld.w Rd, Rb[Ri<<sa]

Rd = *(Rb + (Ri << sa2));

d, p, b, i ∈ {0, 1, …, 15}

Rev1+

6

ld.w Rd, Rb[Ri:<part> << 2]

If (part == b)
     Rd = *(Rb + (Ri[7:0] << 2) );
else if (part == l)
     Rd = *(Rb + (Ri[15:8] << 2) );
else if (part == u)
     Rd = *(Rb + (Ri[23:16] << 2) );
else
     Rd = *(Rb + (Ri[31:24] << 2) );

{d, b, i} ∈ {0, 1, …, 15}
part ∈ {t, u, l, b}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ld.w{cond4} Rd, Rp[disp]

if (cond4)
Rd = *(Rp + (ZE(disp9<<2)));

d, p ∈ {0, 1, …, 15}
disp ∈ {0, 4, ..., 2044}
cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Rev2+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldc.d CP#, CRd, Rp[disp]

CP#(CRd+1:CRd) = *(Rp + (ZE(disp8) << 2));

# ∈ {0, 1, …, 7}

Rev1+

2

ldc.d CP#, CRd, --Rp

Rp = Rp-8;
CP#(CRd+1:CRd) = *(Rp);

# ∈ {0, 1, …, 7}

Rev1+

3

ldc.d CP#, CRd, Rb[Ri<<sa]

CP#(CRd+1:CRd) = *(Rb + (Ri << sa2));

# ∈ {0, 1, …, 7}

Rev1+

4

ldc.w CP#, CRd, Rp[disp]

CP#(CRd) = *(Rp + (ZE(disp8) << 2));

# ∈ {0, 1, …, 7}

Rev1+

5

ldc.w CP#, CRd, --Rp

Rp = Rp-4;
CP#(CRd) = *(Rp);

# ∈ {0, 1, …, 7}

Rev1+

6

ldc.w CP#, CRd, Rb[Ri<<sa]

CP#(CRd) = *(Rb + (Ri << sa2));

# ∈ {0, 1, …, 7}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldc0.d CRd, Rp[disp]

CP0(CRd+1:CRd) = *(Rp + (ZE(disp12) << 2));

p ∈ {0, 1, …, 15}

Rev1+

2

ldc0.w CRd, Rp[disp]

CP0(CRd) = *(Rp + (ZE(disp12) << 2));

p ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldcm.d CP#, Rp{++}, ReglistCPD8

Loadaddress  =Rp;
for (i = 7 to 0)
      if ReglistCPD8[i] == 1 then
            CP#(CR(2*i+1))   =*(Loadaddress++);
            CP#(CR(2*i))   =*(Loadaddress++);
if Opcode[++] == 1 then
      Rp   = Loadaddress;

# ∈ {0, 1, …, 7}
p ∈ {0, 1, …, 15}

Rev1+

2

ldcm.w CP#, Rp{++}, ReglistCPH8

Loadaddress  =Rp;
for (i = 7 to 0)
      if ReglistCPH8[i] == 1 then
            CP#(CRi+8)   =*(Loadaddress++);
if Opcode[++] == 1 then
      Rp   = Loadaddress;

# ∈ {0, 1, …, 7}
p ∈ {0, 1, …, 15}

Rev1+

3

ldcm.w CP#, Rp{++}, ReglistCPL8

Loadaddress  =Rp;
for (i = 7 to 0)
      if ReglistCPL8[i] == 1 then
            CP#(CRi)   =*(Loadaddress++);
if Opcode[++] == 1 then
      Rp   = Loadaddress;

# ∈ {0, 1, …, 7}
p ∈ {0, 1, …, 15}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

lddpc Rd, PC[disp]

Rd = *( (PC && 0xFFFF_FFFC) + (ZE(disp7) << 2));

d ∈ {0, 1, …, 15}
disp ∈ {0, 4, …, 508}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

lddsp Rd, SP[disp]

Rd = *( (SP && 0xFFFF_FFFC) + (ZE(disp7) << 2));

d ∈ {0, 1, …, 15}
disp ∈ {0, 4, …, 508}

Rev1+

Q:

Not affected.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldins.b Rd:<part>, Rp[disp]

If (part == b)
      Rd[7:0] = *(Rp+SE(disp12));
else if (part == l)
      Rd[15:8] = *(Rp+SE(disp12));
else if (part == u)
      Rd[23:16] = *(Rp+SE(disp12));
else
      Rd[31:24] = *(Rp+SE(disp12));

{p, d} ∈ {0, 1, …, 15}
part ∈ {t, u, l, b}
disp ∈ {-2048, -2047, ..., 2047}

Rev1+

2

ldins.h Rd:<part>, Rp[disp]

If (part == b)
      Rd[15:0] = *(Rp+SE(disp12) << 1);
else
      Rd[31:16] = *(Rp+SE(disp12) << 1);

{p, d} ∈ {0, 1, …, 15}
part ∈ {t, b}
disp ∈ {-4096, -4094, ..., 4094}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldm Rp{++}, Reglist16

Loadaddress  = Rp;
if Reglist16[PC] == 1 then 
      if Rp == PC then
            Loadaddress = SP;
      PC = *(Loadaddress++);
      if Rp == PC then
            if Reglist16[LR,R12] == B'00
                  R12   =   0;
            else if Reglist16[LR,R12] == B'01
                  R12   =   1;
            else
                  R12   =    - 1;
            Test R12 and update flags;
      else
            if Reglist16[LR] == 1
                  LR = *(Loadaddress++);
            if Reglist16[SP] == 1
                  SP = *(Loadaddress++);
            if Reglist16[R12] == 1
                  R12 =  *(Loadaddress++);
            Test R12 and update flags;
else
      if Reglist16[LR] == 1
            LR = *(Loadaddress++);
      if Reglist16[SP] == 1
            SP = *(Loadaddress++);
      if Reglist16[R12] == 1
            R12 =  *(Loadaddress++);
for (i = 11 to 0)
      if Reglist16[i] == 1 then
            Ri   =
                  *(Loadaddress++);
if Opcode[++] == 1 then
      if Rp == PC then
            SP   = Loadaddress;
      else
            Rp   = Loadaddress;

Reglist16 ∈ {R0, R1, R2, ..., R12, LR, SP, PC} 
p ∈ {0, 1, …, 15}

Rev1+

Flags are only updated if Reglist16[PC] == 1.

They are set as the result of the operation cp R12, 0.

Q:

Not affected

V:

V = 0

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

C = 0

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldmts Rp{++}, Reglist16

Loadaddress  =Rp;
for (i = 15 to 0)
      if Reglist16[i] == 1 then
            Ri USER  =*(Loadaddress++);
if Opcode[++] == 1 then
      Rp   = Loadaddress;

Reglist16 ∈ {R0, R1, R2, ..., R12, LR, SP} 
p ∈ {0, 1, …, 15}

Rev1+

Not affected.

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldswp.shRd, Rp[disp]

temp[15:0] = *(Rp+SE(disp12) << 1);
Rd = SE(temp[7:0], temp[15:8]);

{d, p} ∈ {0, 1, …, 15}
disp ∈ {-4096, -4094, ..., 4094}

Rev1+

2

ldswp.uhRd, Rp[disp]

temp[15:0] = *(Rp+SE(disp12) << 1);
Rd = ZE(temp[7:0], temp[15:8]);

{d, p} ∈ {0, 1, …, 15}
disp ∈ {-4096, -4094, ..., 4094}

Rev1+

3

ldswp.wRd, Rp[disp]

temp = *(Rp+SE(disp12) << 2);
Rd = (temp[7:0], temp[15:8], temp[23:16], temp[31:24]);

{d, p} ∈ {0, 1, …, 15}
disp ∈ {-8192, -8188, ..., 8188}

Rev1+

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

lsl Rd, Rx, Ry

Rd = LSL(Rx, Ry[4:0]);

{d, x, y} ∈ {0, 1, …, 15}

Rev1+

2

lsl Rd, sa

Rd = LSL(Rd, sa5);

d ∈ {0, 1, …, 15}
sa  ∈ {0, 1, …, 31}

Rev1+

3

lsl Rd, Rs, sa

Rd = LSL(Rs, sa5);

{d,s} ∈ {0, 1, …, 15}
sa  ∈ {0, 1, …, 31}

Rev1+

Format I: Shamt = Ry[4:0], Op = Rx

Format II: Shamt = sa5, Op = Rd

Format III: Shamt = sa5, Op = Rs

Q:

Not affected

V:

Not affected

N:

N = RES[31]

Z:

Z = (RES[31:0] == 0)

C:

if Shamt != 0

C = Op[32-Shamt]

else

C = 0

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

lsr Rd, Rx, Ry

Rd = LSR(Rx, Ry[4:0]);

{d, x, y} ∈ {0, 1, …, 15}

Rev1+

2

lsr Rd, sa

Rd = LSR(Rd, sa5);

d ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}

Rev1+