Opcode/ Instruction |
Op/ En |
64/32 bit Mode Support |
CPUID Feature Flag |
Description |
EVEX.LLIG.F3.MAP5.W0 5A /r VCVTSH2SD xmm1{k1}{z}, xmm2, xmm3/m16 {sae} |
A |
V/V |
AVX512-FP16 |
Convert the low FP16 value in xmm3/m16 to an FP64 value and store the result in the low element of xmm1 subject to writemask k1. Bits 127:64 of xmm2 are copied to xmm1[127:64]. |
Op/En |
Tuple |
Operand 1 |
Operand 2 |
Operand 3 |
Operand 4 |
A |
Scalar |
ModRM:reg (w) |
VEX.vvvv (r) |
ModRM:r/m (r) |
N/A |
This instruction converts the low FP16 element in the second source operand to a FP64 element in the low element of the destination operand.
Bits 127:64 of the destination operand are copied from the corresponding bits of the first source operand. Bits MAXVL-1:128 of the destination operand are zeroed. The low FP64 element of the destination is updated according to the writemask.
IF k1[0] OR *no writemask*: DEST.fp64[0] := Convert_fp16_to_fp64(SRC2.fp16[0]) ELSE IF *zeroing*: DEST.fp64[0] := 0 // else dest.fp64[0] remains unchanged DEST[127:64] := SRC1[127:64] DEST[MAXVL-1:128] := 0
VCVTSH2SD __m128d _mm_cvt_roundsh_sd (__m128d a, __m128h b, const int sae); VCVTSH2SD __m128d _mm_mask_cvt_roundsh_sd (__m128d src, __mmask8 k, __m128d a, __m128h b, const int sae); VCVTSH2SD __m128d _mm_maskz_cvt_roundsh_sd (__mmask8 k, __m128d a, __m128h b, const int sae); VCVTSH2SD __m128d _mm_cvtsh_sd (__m128d a, __m128h b); VCVTSH2SD __m128d _mm_mask_cvtsh_sd (__m128d src, __mmask8 k, __m128d a, __m128h b); VCVTSH2SD __m128d _mm_maskz_cvtsh_sd (__mmask8 k, __m128d a, __m128h b);
Invalid, Denormal.
EVEX-encoded instructions, see Table 2-47, "Type E3 Class Exception Conditions."