Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment:

Stack

ST Y, Rr

DS(Y) = Rr

0 <= r <= 31

PC = PC + 1

1000001rrrrr1000

Y: Unchanged

ST Y+, Rr

DS(Y) = Rr, Y = Y+1

0 <= r <= 31

PC = PC + 1

1001001rrrrr1001

Y: Post incremented

ST -Y, Rr

Y = Y - 1, DS(Y) = Rr

0 <= r <= 31

PC = PC + 1

1001001rrrrr1010

Y: Pre decremented

STD Y+q, Rr

DS(Y+q) = Rr

0 <= r <= 31, 0 <= q <= 63

PC = PC + 1

10q0qq1rrrrr1qqq

Y: Unchanged, q: Displacement

Description

Stores one byte indirect with or without displacement from a register to data space. The data space usually consists of the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.

The data location is pointed to by the Y (16-bit) Pointer Register in the Register File. Memory access is limited to the current data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the RAMPY in the register in the I/O area has to be changed.

The Y-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre- decremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the Y-Pointer Register. Note that only the low byte of the Y-pointer is updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPY Register in the I/O area is updated in parts with more than 64 KB data space or more than 64 KB program memory, and the increment/ decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction are available on all devices.

The result of these combinations is undefined:

ST Y+, r28

ST Y+, r29

ST -Y, r28

ST -Y, r29

Using the Y-pointer:

Status Register (SREG) and Boolean Formula

I

–

T

–

H

–

S

–

V

–

N

–

Z

–

C

–

Example: 

      clr   r29       ; Clear Y high byte
      ldi   r28,0x60  ; Set Y low byte to 0x60
      st    Y+,r0     ; Store r0 in data space loc. 0x60(Y post inc)
      st    Y,r1      ; Store r1 in data space loc. 0x61
      ldi   r28,0x63  ; Set Y low byte to 0x63
      st    Y,r2      ; Store r2 in data space loc. 0x63
      st    -Y,r3     ; Store r3 in data space loc. 0x62(Y pre dec)
      std   Y+2,r4    ; Store r4 in data space loc. 0x64

Words

1 (2 bytes)

Table Cycles

Name

Cycles

(i)

(ii)

(iii)

(iv)

AVRe

2(1)

2(1)

2(1)

2(1)

AVRxm

1(1)

1(1)

2(1)

2(1)

AVRxt

1(2)

1(2)

1(2)

1(2)

AVRrc

1

1

2

N/A

Notes:

1.

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

2.

Cycle time for data memory access assumes internal RAM access, and are not valid for access to NVM. A minimum of one extra cycle must be added when accessing NVM. The additional time varies dependent on the NVM module implementation. See the NVMCTRL section in the specific devices data sheet for more information.