Syntax: |
Operation: |
Operands: |
Program Counter: |
Opcode |
Comment: |
Stack: |
RETI |
PC(15:0) = STACK |
None |
See Operation |
1001010100011000 |
Devices with 16-bit PC, 128 KB program memory maximum. |
SP = SP + 2 (2 bytes, 16 bits) |
RETI |
PC(21:0) = STACK |
None |
See Operation |
1001010100011000 |
Devices with 22-bit PC, 8 MB program memory maximum. |
SP = SP + 3 (3 bytes, 22 bits) |
Returns from the interrupt. The return address is loaded from the STACK, and the Global Interrupt Enable bit is set.
Note that the Status Register is not automatically stored when entering an interrupt routine, and it is not restored when returning from an interrupt routine. This must be handled by the application program. The Stack Pointer uses a pre-increment scheme during RETI.
I |
1 |
1 |
The I flag is set. |
T |
– |
||
H |
– |
||
S |
– |
||
V |
– |
||
N |
– |
||
Z |
– |
||
C |
– |
... extint: push r0 ; Save r0 on the Stack ... pop r0 ; Restore r0 reti ; Return and enable interrupts
1 (2 bytes)
Name |
Cycles 9/16-bit PC |
22-bit PC |
AVRe |
4(2) |
5(2) |
AVRxm |
4(2) |
5(2) |
AVRxt |
4 |
5 |
AVRrc |
6 |
N/A |
Notes:
1.
RETI behaves differently in AVRe, AVRxm, and AVRxt devices. In the AVRe series of devices, the Global Interrupt Enable bit is cleared by hardware once an interrupt occurs, and this bit is set when RETI is executed. In the AVRxm and AVRxt devices, RETI will not modify the Global Interrupt Enable bit in SREG since it is not cleared by hardware while entering ISR. This bit should be modified using SEI and CLI instructions when needed.
2.
Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.