Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment:

Stack

LPM

R0 = PS(Z)

None, R0 implied

PC = PC + 1

1001010111001000

Z: Unchanged, R0 implied destination register

LPM Rd, Z

Rd = PS(Z)

0 <= d <= 31

PC = PC + 1

1001000ddddd0100

Z: Unchanged

LPM Rd, Z+

Rd = PS(Z) Z = Z + 1

0 <= d <= 31

PC = PC + 1

1001000ddddd0101

Z: Post incremented

Description

Loads one byte pointed to by the Z-register into the destination register Rd. This instruction features a 100% space-effective constant initialization or constant data fetch. The program memory is organized in 16-bit words while the Z-pointer is a byte address. Thus, the least significant bit of the Z-pointer selects either low byte (ZLSb == 0) or

high byte (ZLSb == 1). This instruction can address the first 64 KB (32K words) of program memory. The Z-Pointer

Register can either be left unchanged by the operation, or it can be incremented. The incrementation does not apply to the RAMPZ Register.

Devices with self-programming capability can use the LPM instruction to read the Fuse and Lock bit values. Refer to the device documentation for a detailed description.

The LPM instruction is not available on all devices. Refer to Appendix A.

The result of these combinations is undefined:

LPM r30, Z+

LPM r31, Z+

Status Register (SREG) and Boolean Formula

I

–

T

–

H

–

S

–

V

–

N

–

Z

–

C

–

Example: 

      ldi   ZH, high(Table_1<<1)  ; Initialize Z-pointer
      ldi   ZL, low(Table_1<<1)
      lpm   r16, Z                ; Load constant from Program
                                  ; Memory pointed to by Z (r31:r30)
      ...
Table_1:
      dw    0x5876                ; 0x76 is addresses when Z_LSB == 0
                                  ; 0x58 is addresses when Z_LSB == 1
      ...

Words

1 (2 bytes)

Table Cycles

Name

Cycles

AVRe

3

AVRxm

3

AVRxt

3

AVRrc

N/A