Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

INC Rd

Rd = Rd + 1

0 <= d <= 31

PC = PC + 1

1001010ddddd0011

Description

Adds one -1- to the contents of register Rd and places the result in the destination register Rd.

The C flag in SREG is not affected by the operation, thus allowing the INC instruction to be used on a loop counter in multiple-precision computations.

When operating on unsigned numbers, only BREQ and BRNE branches can be expected to perform consistently. When operating on two's complement values, all signed branches are available.

Status Register and Boolean Formula

I

–

T

–

H

–

S

⇔

N XOR V, for signed tests.

V

⇔

R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0

Set if two's complement overflow resulted from the operation; cleared otherwise. Two's complement overflow

occurs only if Rd was 0x7F before the operation.

N

⇔

R7

Set if MSB of the result is set; cleared otherwise.

Z

⇔

~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0

Set if the result is 0x00; cleared otherwise.

C

–

R (Result)

R (Result) equals Rd after the operation.

Example: 

      clr   r22       ; clear r22
loop: 
      inc   r22       ; increment r22
      ...
      cpi   r22,0x4F  ; Compare r22 to 0x4f
      brne  loop      ; Branch if not equal
      nop             ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name

Cycles

AVRe

1

AVRxm

1

AVRxt

1

AVRrc

1