Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment:

Stack

ELPM

R0 = PS(RAMPZ:Z)

None, R0 implied

PC = PC + 1

1001010111011000

RAMPZ:Z: Unchanged, R0 implied destination register

ELPM Rd, Z

Rd = PS(RAMPZ:Z)

0 <= d <= 31

PC = PC + 1

1001000ddddd0110

RAMPZ:Z: Unchanged

ELPM Rd, Z+

Rd = PS(RAMPZ:Z)

0 <= d <= 31

PC = PC + 1

1001000ddddd0111

(RAMPZ:Z) = (RAMPZ:Z) + 1 RAMPZ:Z: Post incremented

Description

Loads one byte pointed to by the Z-register and the RAMPZ Register in the I/O space, and places this byte in the destination register Rd. This instruction features a 100% space-effective constant initialization or constant data fetch. The program memory is organized in 16-bit words while the Z-pointer is a byte address. Thus, the least significant bit of the Z-pointer selects either low byte (ZLSB == 0) or high byte (ZLSB == 1). This instruction can address the

entire program memory space. The Z-Pointer Register can either be left unchanged by the operation, or it can be incremented. The incrementation applies to the entire 24-bit concatenation of the RAMPZ and Z-Pointer Registers.

Devices with self-programming capability can use the ELPM instruction to read the Fuse and Lock bit value. Refer to the device documentation for a detailed description.

This instruction is not available on all devices. Refer to Appendix A.

The result of these combinations is undefined:

ELPM r30, Z+

ELPM r31, Z+

Status Register (SREG) and Boolean Formula

I

–

T

–

H

–

S

–

V

–

N

–

Z

–

C

–

Example: 

      ldi   ZL, byte3(Table_1 << 1)  ; Initialize Z-pointer
      out   RAMPZ, ZL
      ldi   ZH, byte2(Table_1 << 1)
      ldi   ZL, byte1(Table_1 << 1)
      elpm  r16, Z+                  ; Load constant from Program
                                     ; memory pointed to by RAMPZ:Z (Z is r31:r30)
      ...
Table_1:
      dw    0x3738                   ; 0x38 is addressed when Z_LSB == 0
                                     ; 0x37 is addressed when Z_LSB == 1
      ...

Words

1 (2 bytes)

Table Cycles

Name

Cycles

AVRe

3

AVRxm

3

AVRxt

3

AVRrc

N/A