Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

CLI

I = 0

None

PC = PC + 1

1001010011111000

Description

Clears the Global Interrupt Enable (I) bit in SREG (Status Register). The interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. (Equivalent to instruction BCLR 7.)

Status Register (SREG) and Boolean Formula

I

0

0

Global Interrupt Enable bit cleared.

T

–

H

–

S

–

V

–

N

–

Z

–

C

–

Example: 

      in    temp, SREG   ; Store SREG value (temp must be defined by user)
      cli                ; Disable interrupts during timed sequence
      sbi   EECR, EEMWE  ; Start EEPROM write
      sbi   EECR, EEWE
      out   SREG, temp   ; Restore SREG value (I-flag)

Words

1 (2 bytes)

Table Cycles

Name

Cycles

AVRe

1

AVRxm

1

AVRxt

1

AVRrc

1