Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

ASR Rd

Rd = ASR(Rd)

0 <= d <= 31

PC = PC + 1

1001010ddddd0101

Description

Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C flag of the SREG. This operation effectively divides a signed value by two without changing its sign. The Carry flag can be used to round the result.

Status Register (SREG) and Boolean Formula

I

–

T

–

H

–

S

⇔

N XOR V, for signed tests.

V

⇔

N XOR C, for N and C after the shift.

N

⇔

R7. Set if MSB of the result is set; cleared otherwise.

Z

⇔

~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0

Set if the result is 0x00; cleared otherwise.

C

⇔

Rd0

Set if, before the shift, the LSB of Rd was set; cleared otherwise.

R (Result)

R (Result) equals Rd after the operation.

Example: 

      ldi   r16,0x10  ; Load decimal 16 into r16
      asr   r16       ; r16=r16 / 2
      ldi   r17,0xFC  ; Load -4 in r17
      asr   r17       ; r17=r17/2

Words

1 (2 bytes)

Table Cycles

Name

Cycles

AVRe

1

AVRxm

1

AVRxt

1

AVRrc

1