Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

ADC Rd,Rr

Rd = Rd + Rr + C

0 <= d <= 31, 0 <= r <= 31

PC = PC + 1

000111rdddddrrrr

Description

Adds two registers and the contents of the C flag and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I

–

T

–

H

⇔

Rd3 AND Rr3 OR Rr3 AND ~R3 OR ~R3 AND Rd3

Set if there was a carry from bit 3; cleared otherwise.

S

⇔

N XOR V, for signed tests.

V

⇔

Rd7 AND Rr7 AND ~R7 OR ~Rd7 AND ~Rr7 AND R7

Set if two's complement overflow resulted from the operation; cleared otherwise.

N

⇔

R7

Set if MSB of the result is set; cleared otherwise.

Z

⇔

~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0

Set if the result is 0x00; cleared otherwise.

C

⇔

Rd7 AND Rr7 OR Rr7 AND ~R7 OR ~R7 AND Rd7

Set if there was a carry from the MSB of the result; cleared otherwise.

R (Result)

R (Result) equals Rd after the operation.

Example: 

                        ; Add R1:R0 to R3:R2
      add   r2,r0       ; Add low byte
      adc   r3,r1       ; Add with carry high byte

Words

1 (2 bytes)

Table Cycles

Name

Cycles

AVRe

1

AVRxm

1

AVRxt

1

AVRrc

1