AVR8 ISA Reference

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
ADC Rd,Rr	Rd = Rd + Rr + C	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	000111rdddddrrrr

Description

Adds two registers and the contents of the C flag and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	Rd3 AND Rr3 OR Rr3 AND ~R3 OR ~R3 AND Rd3	Set if there was a carry from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	Rd7 AND Rr7 AND ~R7 OR ~Rd7 AND ~Rr7 AND R7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	Rd7 AND Rr7 OR Rr7 AND ~R7 OR ~R7 AND Rd7	Set if there was a carry from the MSB of the result; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

                        ; Add R1:R0 to R3:R2
      add   r2,r0       ; Add low byte
      adc   r3,r1       ; Add with carry high byte

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
ADD Rd,Rr	Rd = Rd + Rr	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	000011rdddddrrrr

Description

Adds two registers without the C flag and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	Rd3 AND Rr3 OR Rr3 AND ~R3 OR ~R3 AND Rd3	Set if there was a carry from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	Rd7 AND Rr7 AND ~R7 OR ~Rd7 AND ~Rr7 AND R7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	Rd7 AND Rr7 OR Rr7 AND ~R7 OR ~R7 AND Rd7	Set if there was a carry from the MSB of the result; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

      add   r1,r2       ; Add r2 to r1 (r1=r1+r2)
      add   r28,r28     ; Add r28 to itself (r28=r28+r28)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
ADIW Rd,K	R[d+1]:Rd = R[d+1]:Rd + K	d ∈ {24,26,28,30}, 0 <= K <= 63	PC = PC + 1	10010110KKddKKKK

Description

Adds an immediate value (0-63) to a register pair and places the result in the register pair. This instruction operates on the upper four register pairs and is well suited for operations on the Pointer Registers.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	⇔	~Rdh7 AND R15	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R15	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R15 AND ~R14 AND ~R13 AND ~R12 AND ~R11 AND ~R10 AND ~R9 AND ~R8 ANDR7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x0000; cleared otherwise.
C	⇔	~R15 AND Rdh7	Set if there was a carry from the MSB of the result; cleared otherwise.
R (Result)	R (Result) equals R[d+1]:Rd after the operation.

Example:

      adiw      r24,1      ; Add 1 to r25:r24
      adiw      ZL,63      ; Add 63 to the Z-pointer(r31:r30)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
ANDI Rd,K	Rd = Rd AND K	16 <= d <= 31, 0 <= K <= 255	PC = PC + 1	0111KKKKddddKKKK

Description

Performs the logical AND between the contents of register Rd and a constant, and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	0	0	Cleared.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      andi  r17,0x0F      ; Clear upper nibble of r17
      andi  r18,0x10      ; Isolate bit 4 in r18
      andi  r19,0xAA      ; Clear odd bits of r19

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
AND Rd,Rr	Rd = Rd AND Rr	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	001000rdddddrrrr

Description

Performs the logical AND between the contents of register Rd and register Rr, and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	0	0	Cleared.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      and   r2,r3     ; Bitwise and r2 and r3, result in r2
      ldi   r16,1     ; Set bitmask 0000 0001 in r16
      and   r2,r16    ; Isolate bit 0 in r2

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
ASR Rd	Rd = ASR(Rd)	0 <= d <= 31	PC = PC + 1	1001010ddddd0101

Description

Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C flag of the SREG. This operation effectively divides a signed value by two without changing its sign. The Carry flag can be used to round the result.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	⇔	N XOR C, for N and C after the shift.
N	⇔	R7. Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	Rd0	Set if, before the shift, the LSB of Rd was set; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

      ldi   r16,0x10  ; Load decimal 16 into r16
      asr   r16       ; r16=r16 / 2
      ldi   r17,0xFC  ; Load -4 in r17
      asr   r17       ; r17=r17/2

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
BCLR s	SREG(s) = 0	0 <= s <= 7	PC = PC + 1	100101001sss1000

Description

Clears a single flag in SREG.

Status Register (SREG) and Boolean Formula

I	⇔	If (s == 7) then I = 0, else unchanged.
T	⇔	If (s == 6) then T = 0, else unchanged.
H	⇔	If (s == 5) then H = 0, else unchanged.
S	⇔	If (s == 4) then S = 0, else unchanged.
V	⇔	If (s == 3) then V = 0, else unchanged.
N	⇔	If (s == 2) then N = 0, else unchanged.
Z	⇔	If (s == 1) then Z = 0, else unchanged.
C	⇔	If (s == 0) then C = 0, else unchanged.

Example:

      bclr  0  ; Clear Carry flag
      bclr  7  ; Disable interrupts

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
BLD Rd,b	Rd(b) = T	0 <= d <= 31, 0 <= b <= 7	PC = PC + 1	1111100ddddd0bbb

Description

Copies the T bit in the SREG (Status Register) to bit b in register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

                  ; Copy bit
      bst   r1,2  ; Store bit 2 of r1 in T bit
      bld   r0,4  ; Load T bit into bit 4 of r0

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRrc	1
AVRe	1
AVRxm	1
AVRxt	1

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRBC s,k

If SREG(s) == 0 then PC = PC + k + 1, else PC = PC + 1

0 <= s <= 7, -64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkksss

Description

Conditional relative branch. Tests a single bit in SREG and branches relatively to the PC if the bit is cleared. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        cpi   r20,5     ; Compare r20 to the value 5
        brbc  1,noteq   ; Branch if Zero flag cleared
        ...
noteq:  nop             ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRBS s,k

If SREG(s) == 1 then PC = PC + k + 1, else PC = PC + 1

0 <= s <= 7, -64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkksss

Description

Conditional relative branch. Tests a single bit in SREG and branches relatively to the PC if the bit is set. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        bst   r0,3      ; Load T bit with bit 3 of r0
        brbs  6,bitset  ; Branch T bit was set
        ...
bitset: nop             ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRCC k

If C == 0 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkk000

Description

Conditional relative branch. Tests the Carry (C) flag and branches relatively to the PC if C is cleared. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBC 0,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

          add   r22,r23  ; Add r23 to r22
          brcc  nocarry  ; Branch if carry cleared
          ...
nocarry:  nop            ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRCS k

If C == 1 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkk000

Description

Conditional relative branch. Tests the Carry (C) flag and branches relatively to the PC if C is set. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBS 0,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        cpi   r26,0x56  ; Compare r26 with 0x56
        brcs  carry     ; Branch if carry set
        ...
carry:  nop             ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
BREAK	On-chip Debug system breakpoint instruction.	None	PC = PC + 1	1001010110011000

Description

The BREAK instruction is used by the On-chip Debug system and not used by the application software. When the BREAK instruction is executed, the AVR CPU is set in the Stopped state. This gives the On-chip Debugger access to internal resources.

If the device is locked, or the on-chip debug system is not enabled, the CPU will treat the BREAK instruction as a NOP and will not enter the Stopped state.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BREQ k

If Rd == Rr (Z == 1) then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkk001

Description

Conditional relative branch. Tests the Zero (Z) flag and branches relatively to the PC if Z is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the unsigned or signed binary number represented in Rd was equal to the unsigned or signed binary number represented in Rr. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBS 1,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        cp    r1,r0  ; Compare registers r1 and r0
        breq  equal  ; Branch if registers equal
        ...
equal:  nop          ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRGE k

If Rd >= Rr (S == 0) then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkk100

Description

Conditional relative branch. Tests the Sign (S) flag and branches relatively to the PC if S is cleared. If the instruction is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the signed binary number represented in Rd was greater than or equal to the signed binary number represented in Rr. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBC 4,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

          cp    r11,r12  ; Compare registers r11 and r12
          brge  greateq  ; Branch if r11 ≥ r12 (signed)
          ...
greateq:  nop            ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRHC k

If H == 0 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkk101

Description

Conditional relative branch. Tests the Half Carry (H) flag and branches relatively to the PC if H is cleared. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBC 5,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        brhc  hclear  ; Branch if Half Carry flag cleared
        ...
hclear: nop           ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRHS k

If H == 1 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkk101

Description

Conditional relative branch. Tests the Half Carry (H) flag and branches relatively to the PC if H is set. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBS 5,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      brhs  hset  ; Branch if Half Carry flag set
      ...
hset: nop         ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRID k

If I == 0 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkk111

Description

Conditional relative branch. Tests the Global Interrupt Enable (I) bit and branches relatively to the PC if I is cleared. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBC 7,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        brid  intdis  ; Branch if interrupt disabled
        ... 
intdis: nop           ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRIE k

If I == 1 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkk111

Description

Conditional relative branch. Tests the Global Interrupt Enable (I) bit and branches relatively to the PC if I is set. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBS 7,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        brie  inten  ; Branch if interrupt enabled
        ... 
inten:  nop          ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRLO k

If Rd < Rr (C == 1) then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkk000

Description

Conditional relative branch. Tests the Carry (C) flag and branches relatively to the PC if C is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the unsigned binary number represented in Rd was smaller than the unsigned binary number represented in Rr. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBS 0,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      eor   r19,r19   ; Clear r19
loop: inc   r19       ; Increase r19
      ...
      cpi   r19,0x10  ; Compare r19 with 0x10
      brlo  loop      ; Branch if r19 < 0x10 (unsigned)
      nop             ; Exit from loop (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRLT k

If Rd < Rr (S == 1) then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkk100

Description

Conditional relative branch. Tests the Sign (S) flag and branches relatively to the PC if S is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the signed binary number represented in Rd was less than the signed binary number represented in Rr. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBS 4,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      cp    r16,r1  ; Compare r16 to r1
      brlt  less    ; Branch if r16 < r1 (signed)
      ...
less: nop           ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRMI k

If N == 1 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkk010

Description

Conditional relative branch. Tests the Negative (N) flag and branches relatively to the PC if N is set. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBS 2,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

          subi r18,4     ; Subtract 4 from r18
          brmi negative  ; Branch if result negative
          ...
negative: nop            ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRNE k

If Rd != Rr (Z == 0) then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkk001

Description

Conditional relative branch. Tests the Zero (Z) flag and branches relatively to the PC if Z is cleared. If the instruction is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the unsigned or signed binary number represented in Rd was not equal to the unsigned or signed binary number represented in Rr. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBC 1,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      eor r27,r27  ; Clear r27
loop: inc r27      ; Increase r27
      ... 
      cpi r27,5    ; Compare r27 to 5
      brne loop    ; Branch if r27<>5
      nop          ; Loop exit (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRPL k

If N == 0 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkk010

Description

Conditional relative branch. Tests the Negative (N) flag and branches relatively to the PC if N is cleared. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBC 2,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

          subi  r26,0x50  ; Subtract 0x50 from r26
          brpl  positive  ; Branch if r26 positive
          ...
positive: nop             ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRSH k

If Rd >=Rr (C == 0) then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkk000

Description

Conditional relative branch. Tests the Carry (C) flag and branches relatively to the PC if C is cleared. If the instruction is executed immediately after execution of any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the unsigned binary number represented in Rd was greater than or equal to the unsigned binary number represented in Rr. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBC 0,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        subi  r19,4   ; Subtract 4 from r19
        brsh  highsm  ; Branch if r19 >= 4 (unsigned)
        ...
highsm: nop           ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRTC k

If T == 0 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkk110

Description

Conditional relative branch. Tests the T bit and branches relatively to the PC if T is cleared. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBC 6,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        bst   r3,5    ; Store bit 5 of r3 in T bit
        brtc  tclear  ; Branch if this bit was cleared
        ...
tclear: nop           ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRTS k

If T == 1 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkk110

Description

Conditional relative branch. Tests the T bit and branches relatively to the PC if T is set. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBS 6,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      bst   r3,5  ; Store bit 5 of r3 in T bit
      brts  tset  ; Branch if this bit was set
      ...
tset: nop         ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRVC k

If V == 0 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111101kkkkkkk011

Description

Conditional relative branch. Tests the Overflow (V) flag and branches relatively to the PC if V is cleared. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBC 3,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        add   r3,r4   ; Add r4 to r3
        brvc  noover  ; Branch if no overflow
        ...
noover: nop           ; Branch destination (do nothing)

Words

1 (2 bytes)

i) If the condition is false.

ii) If the condition is true.

Table Cycles

Name	Cycles i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

BRVS k

If V == 1 then PC = PC + k + 1, else PC = PC + 1

-64 <= k <= +63

PC = PC + k + 1

PC = PC + 1, if the condition is false

111100kkkkkkk011

Description

Conditional relative branch. Tests the Overflow (V) flag and branches relatively to the PC if V is set. This instruction branches relatively to the PC in either direction (PC - 63 <= destination <= PC + 64). Parameter k is the offset from the PC and is represented in two's complement form. (Equivalent to instruction BRBS 3,k.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        add   r3,r4   ; Add r4 to r3
        brvs  overfl  ; Branch if overflow
        ...
overfl: nop           ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii
AVRxt	1	2
AVRrc	1	2
AVRe	1	2
AVRxm	1	2

i) If the condition is false.

ii) If the condition is true.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
BSET s	SREG(s) = 1	0 <= s <= 7	PC = PC + 1	100101000sss1000

Description

Sets a single flag or bit in SREG.

Status Register (SREG) and Boolean Formula

I	⇔	If (s == 7) then I = 1, else unchanged.
T	⇔	If (s == 6) then T = 1, else unchanged.
H	⇔	If (s == 5) then H = 1, else unchanged.
S	⇔	If (s == 4) then S = 1, else unchanged.
V	⇔	If (s == 3) then V = 1, else unchanged.
N	⇔	If (s == 2) then N = 1, else unchanged.
Z	⇔	If (s == 1) then Z = 1, else unchanged.
C	⇔	If (s == 0) then C = 1, else unchanged.

Example:

      bset  6  ; Set T bit
      bset  7  ; Enable interrupt

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
BST Rd,b	T = Rd(b)	0 <= d <= 31, 0 <= b <= 7	PC = PC + 1	1111101ddddd0bbb

Description

Stores bit b from Rd to the T bit in SREG (Status Register).

Status Register (SREG) and Boolean Formula

I	–
T	⇔	‘0' if bit b in Rd is cleared. Set to ‘1' otherwise.
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

                  ; Copy bit
      bst   r1,2  ; Store bit 2 of r1 in T bit
      bld   r0,4  ; Load T into bit 4 of r0

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack:

CALL k

PC = k Devices with 16-bit PC, 128 KB program memory maximum.

0 <= k < 64K

PC = k

1001010kkkkk111kkkkkkkkkkkkkkkkk

STACK = PC+2

SP = SP-2, (2 bytes, 16 bits)

CALL k

PC = k Devices with 22-bit PC, 8 MB program memory maximum.

0 <= k < 4M

PC = k

1001010kkkkk111kkkkkkkkkkkkkkkkk

STACK = PC+2

SP = SP-3 (3 bytes, 22 bits)

Description

Calls to a subroutine within the entire program memory. The return address (to the instruction after the CALL) will be stored on the Stack. (See also RCALL.) The Stack Pointer uses a post-decrement scheme during CALL.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      mov   r16,r0    ; Copy r0 to r16
      call  check     ; Call subroutine
      nop             ; Continue (do nothing)
      ...
check:
      cpi   r16,0x42  ; Check if r16 has a special value
      breq  error     ; Branch if equal
      ret             ; Return from subroutine
      ...
error: 
      rjmp  error     ; Infinite loop

Words

2 (4 bytes)

Table Cycles

Name	Cycles 16-bit PC	22-bit PC
AVRxt	3	4
AVRrc	N/A	N/A
AVRe	4₍₁₎	5₍₁₎
AVRxm	3₍₁₎	4₍₁₎

Note:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CBI A,b	I/O(A,b) = 0	0 <= A <= 31, 0 <= b <= 7	PC = PC + 1	10011000AAAAAbbb

Description

Clears a specified bit in an I/O Register. This instruction operates on the lower 32 I/O Registers - addresses 0-31.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      cbi   0x12,7  ; Clear bit 7 at address 0x12

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CBR Rd,K	Rd = Rd AND (0xFF - K)	16 <= d <= 31, 0 <= K <= 255	PC = PC + 1	16-bit Opcode: (see ANDI with K complemented)

Description

Clears the specified bits in register Rd. Performs the logical AND between the contents of register Rd and the complement of the constant mask K. The result will be placed in register Rd. (Equivalent to ANDI Rd,(0xFF - K).)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	0	0	Cleared.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      cbr   r16,0xF0  ; Clear upper nibble of r16
      cbr   r18,1     ; Clear bit 0 in r18

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CLC	C = 0	None	PC = PC + 1	1001010010001000

Description

Clears the Carry (C) flag in SREG (Status Register). (Equivalent to instruction BCLR 0.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	0	0	Carry flag cleared.

Example:

      add   r0,r0  ; Add r0 to itself
      clc          ; Clear Carry flag

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CLH	H = 0	None	PC = PC + 1	1001010011011000

Description

Clears the Half Carry (H) flag in SREG (Status Register). (Equivalent to instruction BCLR 5.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	0	0	Half Carry flag cleared.
S	–
V	–
N	–
Z	–
C	–

Example:

      clh  ; Clear the Half Carry flag

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CLI	I = 0	None	PC = PC + 1	1001010011111000

Description

Clears the Global Interrupt Enable (I) bit in SREG (Status Register). The interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. (Equivalent to instruction BCLR 7.)

Status Register (SREG) and Boolean Formula

I	0	0	Global Interrupt Enable bit cleared.
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      in    temp, SREG   ; Store SREG value (temp must be defined by user)
      cli                ; Disable interrupts during timed sequence
      sbi   EECR, EEMWE  ; Start EEPROM write
      sbi   EECR, EEWE
      out   SREG, temp   ; Restore SREG value (I-flag)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CLN	N = 0	None	PC = PC + 1	1001010010101000

Description

Clears the Negative (N) flag in SREG (Status Register). (Equivalent to instruction BCLR 2.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	0	0	Negative flag cleared.
Z	–
C	–

Example:

      add   r2,r3  ; Add r3 to r2
      cln          ; Clear Negative flag

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CLR Rd	Rd = Rd XOR Rd	0 <= d <= 31	PC = PC + 1	001001dddddddddd

Description

Clears a register. This instruction performs an Exclusive OR between a register and itself. This will clear all bits in the register. (Equivalent to instruction EOR Rd,Rd.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	0	0	Cleared.
V	0	0	Cleared.
N	0	0	Cleared.
Z	1	1	Set.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      clr   r18       ; clear r18
loop: inc   r18       ; increase r18
      ...
      cpi   r18,0x50  ; Compare r18 to 0x50
      brne  loop

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CLS	S = 0	None	PC = PC + 1	1001010011001000

Description

Clears the Sign (S) flag in SREG (Status Register). (Equivalent to instruction BCLR 4.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	0	0	Sign flag cleared.
V	–
N	–
Z	–
C	–

Example:

      add   r2,r3  ; Add r3 to r2
      cls          ; Clear Sign flag

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CLT	T = 0	None	PC = PC + 1	1001010011101000

Description

Clears the T bit in SREG (Status Register). (Equivalent to instruction BCLR 6.)

Status Register (SREG) and Boolean Formula

I	–
T	0	0	T bit cleared.
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clt  ; Clear T bit

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CLV	V = 0	None	PC = PC + 1	1001010010111000

Description

Clears the Overflow (V) flag in SREG (Status Register). (Equivalent to instruction BCLR 3.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	0	0	Overflow flag cleared.
N	–
Z	–
C	–

Example:

      add   r2,r3  ; Add r3 to r2
      clv          ; Clear Overflow flag

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CLZ	Z = 0	None	PC = PC + 1	1001010010011000

Description

Clears the Zero (Z) flag in SREG (Status Register). (Equivalent to instruction BCLR 1.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	0	0	Zero flag cleared.
C	–

Example:

      add   r2,r3  ; Add r3 to r2
      clz          ; Clear zero

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
COM Rd	Rd = 0xFF - Rd	0 <= d <= 31	PC = PC + 1	1001010ddddd0000

Description

This instruction performs a One's Complement of register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	0	0	Cleared.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	1	1	Set.
R (Result)	R (Result) equals Rd after the operation.

Example:

      com   r4     ; Take one’s complement of r4
      breq  zero   ; Branch if zero
      ...
zero: nop          ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CPC Rd,Rr	Rd - Rr - C	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	000001rdddddrrrr

Description

This instruction performs a compare between two registers Rd and Rr and also takes into account the previous carry. None of the registers are changed. All conditional branches can be used after this instruction.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	~Rd3 AND Rr3 OR Rr3 AND R3 OR R3 AND ~Rd3	Set if there was a borrow from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	Rd7 AND ~Rr7 AND ~R7 OR ~Rd7 AND Rr7 AND R7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0 AND Z	The previous value remains unchanged when the result is zero; cleared otherwise.
C	⇔	~Rd7 AND Rr7 OR Rr7 AND R7 OR R7 AND ~Rd7	Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of Rd; cleared otherwise.
R (Result)	R (Result) after the operation.

Example:

                   ; Compare r3:r2 with r1:r0
      cp    r2,r0  ; Compare low byte
      cpc   r3,r1  ; Compare high byte
      brne  noteq  ; Branch if not equal
      ...
noteq: 
      nop          ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CPI Rd,K	Rd - K	16 <= d <= 31, 0 <= K <= 255	PC = PC + 1	0011KKKKddddKKKK

Description

This instruction performs a compare between register Rd and a constant. The register is not changed. All conditional branches can be used after this instruction.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	~Rd3 AND K3 OR K3 AND R3 OR R3 AND ~Rd3	Set if there was a borrow from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	Rd7 AND ~K7 AND ~R7 OR ~Rd7 AND K7 AND R7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	~Rd7 AND K7 OR K7 AND R7 OR R7 AND ~Rd7	Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.
R (Result)	R (Result) after the operation.

Example:

      cpi   r19,3  ; Compare r19 with 3
      brne  error  ; Branch if r19<>3
      ...
error: 
      nop          ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

CPSE Rd,Rr

If Rd == Rr then PC = PC + 2 (or 3) else PC = PC + 1

0 <= d <= 31, 0 <= r <= 31

PC = PC + 1, Condition false - no skip

PC = PC + 2, Skip a one word instruction

PC = PC + 3, Skip a two word instruction

000100rdddddrrrr

Description

This instruction performs a compare between two registers Rd and Rr and skips the next instruction if Rd == Rr.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      inc   r4     ; Increase r4
      cpse  r4,r0  ; Compare r4 to r0
      neg   r4     ; Only executed if r4<>r0
      nop          ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii
AVRe	1	2	3
AVRxm	1	2	3
AVRxt	1	2	3
AVRrc	1	2	N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
CP Rd,Rr	Rd - Rr	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	000101rdddddrrrr

Description

This instruction performs a compare between two registers Rd and Rr. None of the registers are changed. All conditional branches can be used after this instruction.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	~Rd3 AND Rr3 OR Rr3 AND R3 OR R3 AND ~Rd3	Set if there was a borrow from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	Rd7 AND ~Rr7 AND ~R7 OR ~Rd7 AND Rr7 AND R7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	~Rd7 AND Rr7 OR Rr7 AND R7 OR R7 AND ~Rd7	Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.
R (Result)	R (Result) after the operation.

Example:

      cp    r4,r19  ; Compare r4 with r19
      brne  noteq   ; Branch if r4 <> r19
      ...
noteq: 
      nop           ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
DEC Rd	Rd = Rd - 1	0 <= d <= 31	PC = PC + 1	1001010ddddd1010

Description

Subtracts one -1- from the contents of register Rd and places the result in the destination register Rd.

The C flag in SREG is not affected by the operation, thus allowing the DEC instruction to be used on a loop counter in multiple-precision computations.

When operating on unsigned values, only BREQ and BRNE branches can be expected to perform consistently. When operating on two's complement values, all signed branches are available.

Status Register and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	⇔	~R7 AND R6 AND R5 AND R4 AND R3 AND R2 AND R1 AND R0	Set if two's complement overflow resulted from the operation; cleared otherwise. Two's complement overflow occurs only if Rd was 0x80 before the operation.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      ldi   r17,0x10  ; Load constant in r17
loop:
      add   r1,r2     ; Add r2 to r1
      dec   r17       ; Decrement r17
      brne  loop      ; Branch if r17<>0
      nop             ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

DES K

If H == 0 then Encrypt round (R7-R0, R15-R8, K)

If H == 1 then Decrypt round (R7-R0, R15-R8, K)

0x00<=K<=0x0F

PC = PC + 1

10010100KKKK1011

Description

The module is an instruction set extension to the AVR CPU, performing DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in the CPU Register File, registers R0-R7, where the LSB of data is placed in the LSB of R0 and the MSB of data is placed in the MSB of R7. The full 64-bit key (including parity bits) is placed in registers R8-R15, organized in the Register File with the LSB of the key in the LSB of R8 and the MSB of the key in the MSB of R15. Executing one DES instruction performs one round in the DES algorithm. Sixteen rounds must be executed in increasing order to form the correct DES ciphertext or plaintext. Intermediate results are stored in the Register File (R0-R15) after each DES instruction. The instruction's operand (K) determines which round is executed, and the Half Carry (H) flag determines whether encryption or decryption is performed.

The DES algorithm is described in "Specifications for the Data Encryption Standard" (Federal Information Processing Standards Publication 46). Intermediate results in this implementation differ from the standard because the initial permutation and the inverse initial permutation are performed in each iteration. This does not affect the result in the final ciphertext or plaintext but reduces the execution time.

Example:

      des   0x00
      des   0x01
      …
      des   0x0E
      des   0x0F

Words

1 (2 bytes)

Table Cycles

Name Note: If the DES instruction is succeeding a non-DES instruction, it requires two cycles otherwise one.	Cycles
AVRe	N/A
AVRxm	1 / 2
AVRxt	N/A
AVRrc	N/A

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack:

EICALL

PC(15:0) = Z(15:0)

PC(21:16) = EIND

None

See Operation

1001010100011001

STACK = PC + 1

SP = SP - 3 (3 bytes, 22 bits)

Description

Indirect call of a subroutine pointed to by the Z (16-bit) Pointer Register in the Register File and the EIND Register in the I/O space. This instruction allows for indirect calls to the entire 4M (words) program memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme during EICALL.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      ldi   r16,0x05  ; Set up EIND and Z-pointer
      out   EIND,r16
      ldi   r30,0x00
      ldi   r31,0x10
      eicall          ; Call to 0x051000

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	4₍₂₎
AVRxm	3₍₂₎
AVRxt	3
AVRrc	N/A

Notes:

The instruction is only implemented on devices with 22-bit PC

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack:

EIJMP

PC(15:0) = Z(15:0)

PC(21:16) = EIND

None

See Operation

1001010000011001

Not Affected

Description

Indirect jump to the address pointed to by the Z (16-bit) Pointer Register in the Register File and the EIND Register in the I/O space. This instruction allows for indirect jumps to the entire 4M (words) program memory space. See also IJMP.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      ldi   r16,0x05  ; Set up EIND and Z-pointer
      out   EIND,r16  
      ldi   r30,0x00
      ldi   r31,0x10
      eijmp           ; Jump to 0x051000

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack
ELPM	R0 = PS(RAMPZ:Z)	None, R0 implied	PC = PC + 1	1001010111011000	RAMPZ:Z: Unchanged, R0 implied destination register
ELPM Rd, Z	Rd = PS(RAMPZ:Z)	0 <= d <= 31	PC = PC + 1	1001000ddddd0110	RAMPZ:Z: Unchanged
ELPM Rd, Z+	Rd = PS(RAMPZ:Z)	0 <= d <= 31	PC = PC + 1	1001000ddddd0111	(RAMPZ:Z) = (RAMPZ:Z) + 1 RAMPZ:Z: Post incremented

Description

Loads one byte pointed to by the Z-register and the RAMPZ Register in the I/O space, and places this byte in the destination register Rd. This instruction features a 100% space-effective constant initialization or constant data fetch. The program memory is organized in 16-bit words while the Z-pointer is a byte address. Thus, the least significant bit of the Z-pointer selects either low byte (ZLSB == 0) or high byte (ZLSB == 1). This instruction can address the

entire program memory space. The Z-Pointer Register can either be left unchanged by the operation, or it can be incremented. The incrementation applies to the entire 24-bit concatenation of the RAMPZ and Z-Pointer Registers.

Devices with self-programming capability can use the ELPM instruction to read the Fuse and Lock bit value. Refer to the device documentation for a detailed description.

This instruction is not available on all devices. Refer to Appendix A.

The result of these combinations is undefined:

ELPM r30, Z+

ELPM r31, Z+

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      ldi   ZL, byte3(Table_1 << 1)  ; Initialize Z-pointer
      out   RAMPZ, ZL
      ldi   ZH, byte2(Table_1 << 1)
      ldi   ZL, byte1(Table_1 << 1)
      elpm  r16, Z+                  ; Load constant from Program
                                     ; memory pointed to by RAMPZ:Z (Z is r31:r30)
      ...
Table_1:
      dw    0x3738                   ; 0x38 is addressed when Z_LSB == 0
                                     ; 0x37 is addressed when Z_LSB == 1
      ...

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	3
AVRxm	3
AVRxt	3
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
EOR Rd,Rr	Rd = Rd XOR Rr	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	001001rdddddrrrr

Description

Performs the logical EOR between the contents of register Rd and register Rr and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	0	0	Cleared.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      eor   r4,r4    ; Clear r4
      eor   r0,r22   ; Bitwise exclusive or between r0 and r22

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
FMULSU Rd,Rr	R1:R0 = Rd × Rr (signed (1.15) = signed (1.7) × unsigned (1.7))	16 <= d <= 23, 16 <= r <= 23	PC = PC + 1	000000111ddd1rrr

Description

This instruction performs 8-bit × 8-bit -> 16-bit signed multiplication and shifts the result one bit left.

Product High

Product Low

Multiplicand

Multiplier

Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2). (Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMULSU instruction incorporates the shift operation in the same number of cycles as MULSU.

The (1.7) format is most commonly used with signed numbers, while FMULSU performs a multiplication with one unsigned and one signed input. This instruction is, therefore, most useful for calculating two of the partial products when performing a signed multiplication with 16-bit inputs in the (1.15) format, yielding a result in the (1.31) format.

Note: The result of the FMULSU operation may suffer from a 2's complement overflow if interpreted as a number in the (1.15) format. The MSB of the multiplication before shifting must be taken into account and is found in the carry bit. See the following example.

The multiplicand Rd and the multiplier Rr are two registers containing fractional numbers where the implicit radix point lies between bit 6 and bit 7. The multiplicand Rd is a signed fractional number, and the multiplier Rr is an unsigned fractional number. The 16-bit signed fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte).

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	⇔	~R15 AND ~R14 AND ~R13 AND ~R12 AND ~R11 AND ~R10 AND ~R9 AND ~R8 ANDR7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x0000; cleared otherwise.
C	⇔	R16	Set if bit 15 of the result before the left shift is set; cleared otherwise.
R (Result)	R (Result) equals R1,R0 after the operation.

Example:

;******************************************************************************
;* DESCRIPTION
;* Signed fractional multiply of two 16-bit numbers with 32-bit result.
;* USAGE
;* r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1
;******************************************************************************
fmuls16x16_32:
      clr      r2
      fmuls    r23, r21      ; ((signed)ah * (signed)bh) << 1
      movw     r18, r0
      fmul     r22, r20      ; (al * bl) << 1
      adc      r18, r2
      movw     r16, r0
      fmulsu   r23, r20      ; ((signed)ah * bl) << 1
      sbc      r19, r2
      add      r17, r0
      adc      r18, r1
      adc      r19, r2
      fmulsu   r21, r22      ; ((signed)bh * al) << 1
      sbc      r19, r2
      add      r17, r0
      adc      r18, r1
      adc      r19, r2
      ret

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
FMULS Rd,Rr	R1:R0 = Rd × Rr (signed (1.15) = signed (1.7) × signed (1.7))	16 <= d <= 23, 16 <= r <= 23	PC = PC + 1	000000111ddd0rrr

Description

This instruction performs 8-bit × 8-bit -> 16-bit signed multiplication and shifts the result one bit left.

Product High

Product Low

Multiplicand

Multiplier

format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMULS instruction incorporates the shift operation in the same number of cycles as MULS.

The multiplicand Rd and the multiplier Rr are two registers containing signed fractional numbers where the implicit radix point lies between bit 6 and bit 7. The 16-bit signed fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte).

Note: That when multiplying 0x80 (-1) with 0x80 (-1), the result of the shift operation is 0x8000 (-1). The shift operation thus gives a two's complement overflow. This must be checked and handled by software.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	⇔	~R15 AND ~R14 AND ~R13 AND ~R12 AND ~R11 AND ~R10 AND ~R9 AND ~R8 ANDR7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x0000; cleared otherwise.
C	⇔	R16	Set if bit 15 of the result before the left shift is set; cleared otherwise.
R (Result)	R (Result) equals R1,R0 after the operation.

Example:

      fmuls r23,r22     ; Multiply signed r23 and r22 in (1.7) format, 
                        ; result in (1.15) format
      movw  r22,r0      ; Copy result back in r23:r22

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
FMUL Rd,Rr	R1:R0 = Rd × Rr (unsigned (1.15) = unsigned (1.7) × unsigned (1.7))	16 <= d <= 23, 16 <= r <= 23	PC = PC + 1	000000110ddd1rrr

Description

This instruction performs 8-bit × 8-bit -> 16-bit unsigned multiplication and shifts the result one bit left.

Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2). (Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMUL instruction incorporates the shift operation in the same number of cycles as MUL.

The (1.7) format is most commonly used with signed numbers, while FMUL performs an unsigned multiplication. This instruction is, therefore, most useful for calculating one of the partial products when performing a signed multiplication with 16-bit inputs in the (1.15) format, yielding a result in the (1.31) format.

Note: The result of the FMUL operation may suffer from a 2's complement overflow if interpreted as a number in the (1.15) format. The MSB of the multiplication before shifting must be taken into account and is found in the carry bit. See the following example.

The multiplicand Rd and the multiplier Rr are two registers containing unsigned fractional numbers where the implicit radix point lies between bit 6 and bit 7. The 16-bit unsigned fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte).

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	⇔	~R15 AND ~R14 AND ~R13 AND ~R12 AND ~R11 AND ~R10 AND ~R9 AND ~R8 ANDR7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x0000; cleared otherwise.
C	⇔	R16	Set if bit 15 of the result before the left shift is set; cleared otherwise.
R (Result)	R (Result) equals R1,R0 after the operation.

Example:

;******************************************************************************
;* DESCRIPTION
;* Signed fractional multiply of two 16-bit numbers with 32-bit result.
;* USAGE
;* r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1
;******************************************************************************
fmuls16x16_32:
      clr    r2
      fmuls  r23, r21      ; ((signed)ah * (signed)bh) << 1
      movw   r18, r0
      fmul   r22, r20      ; (al * bl) << 1
      adc    r18, r2
      movw   r16, r0
      fmulsu r23, r20      ; ((signed)ah * bl) << 1
      sbc    r19, r2
      add    r17, r0
      adc    r18, r1
      adc    r19, r2
      fmulsu r21, r22      ; ((signed)bh * al) << 1
      sbc    r19, r2
      add    r17, r0
      adc    r18, r1
      adc    r19, r2
      ret

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	N/A

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment:

Stack:

ICALL

PC(15:0) = Z(15:0)

None

See Operation

1001010100001001

Devices with 16-bit PC, 128 KB program memory maximum.

STACK = PC + 1

SP = SP - 2 (2 bytes, 16 bits)

ICALL

PC(15:0) = Z(15:0)

PC(21:16) = 0

None

See Operation

1001010100001001

Devices with 22-bit PC, 8 MB program memory maximum.

STACK = PC + 1

SP = SP - 3 (3 bytes, 22 bits)

Description

Indirect call of a subroutine pointed to by the Z (16-bit) Pointer Register in the Register File. The Z-Pointer Register is 16 bits wide and allows a call to a subroutine within the lowest 64K words (128 KB) section in the program memory space. The Stack Pointer uses a post-decrement scheme during ICALL.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      mov   r30,r0  ; Set offset to call table
      icall         ; Call routine pointed to by r31:r30

Words

1 (2 bytes)

Table Cycles

Name	Cycles 9/16-bit PC	22-bit PC
AVRe	3₍₁₎	4₍₁₎
AVRxm	2₍₁₎	3₍₁₎
AVRxt	2	3
AVRrc	3	N/A

Note:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment:

Stack:

IJMP

PC = Z(15:0)

None

See Operation

1001010000001001

Devices with 16-bit PC, 128 KB program memory maximum.

Not Affected

IJMP

PC(15:0) = Z(15:0)

PC(21:16) = 0

None

See Operation

1001010000001001

Devices with 22-bit PC, 8 MB program memory maximum.

Not Affected

Description

Indirect jump to the address pointed to by the Z (16-bit) Pointer Register in the Register File. The Z-Pointer Register is 16 bits wide and allows jump within the lowest 64K words (128 KB) section of program memory.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      mov   r30,r0  ; Set offset to jump table
      ijmp          ; Jump to routine pointed to by r31:r30

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	2

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
INC Rd	Rd = Rd + 1	0 <= d <= 31	PC = PC + 1	1001010ddddd0011

Description

Adds one -1- to the contents of register Rd and places the result in the destination register Rd.

The C flag in SREG is not affected by the operation, thus allowing the INC instruction to be used on a loop counter in multiple-precision computations.

When operating on unsigned numbers, only BREQ and BRNE branches can be expected to perform consistently. When operating on two's complement values, all signed branches are available.

Status Register and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	⇔	R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if two's complement overflow resulted from the operation; cleared otherwise. Two's complement overflow occurs only if Rd was 0x7F before the operation.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      clr   r22       ; clear r22
loop: 
      inc   r22       ; increment r22
      ...
      cpi   r22,0x4F  ; Compare r22 to 0x4f
      brne  loop      ; Branch if not equal
      nop             ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
IN Rd,A	Rd = I/O(A)	0 <= d <= 31, 0 <= A <= 63	PC = PC + 1	10110AAdddddAAAA

Description

Loads data from the I/O space into register Rd in the Register File.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      in    r25,0x16  ; Read Port B
      cpi   r25,4     ; Compare read value to constant
      breq  exit      ; Branch if r25=4
      ...
exit: 
      nop             ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack:
JMP k	PC = k	0 <= k < 4M	PC = k	1001010kkkkk110kkkkkkkkkkkkkkkkk		Unchanged

Description

Jump to an address within the entire 4M (words) program memory. See also RJMP.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      mov   r1,r0   ; Copy r0 to r1
      jmp   farplc  ; Unconditional jump
      ...
farplc: 
      nop           ; Jump destination (do nothing)

Words

2 (4 bytes)

Table Cycles

Name	Cycles
AVRe	3
AVRxm	3
AVRxt	3
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
LAC Z,Rd	DS(Z) = (0xFF - Rd) AND DS(Z), Rd = DS(Z)	0 <= d <= 31	PC = PC + 1	1001001rrrrr0110

Description

Load one byte indirect from data space to register and stores and clear the bits in data space specified by the register. The instruction can only be used towards internal SRAM.

The data location is pointed to by the Z (16-bit) Pointer Register in the Register File. Memory access is limited to the current data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the RAMPZ in the register in the I/O area has to be changed.

The Z-Pointer Register is left unchanged by the operation. This instruction is especially suited for clearing status bits stored in SRAM.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	N/A
AVRxm	2
AVRxt	N/A
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
LAS Z,Rd	DS(Z) = Rd v DS(Z), Rd = DS(Z)	0 <= d <= 31	PC = PC + 1	1001001rrrrr0101

Description

Load one byte indirect from data space to register and set bits in the data space specified by the register. The instruction can only be used towards internal SRAM.

The Z-Pointer Register is left unchanged by the operation. This instruction is especially suited for setting status bits stored in SRAM.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	N/A
AVRxm	2
AVRxt	N/A
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
LAT Z,Rd	DS(Z) = Rd XOR DS(Z), Rd = DS(Z)	0 <= d <= 31	PC = PC + 1	1001001rrrrr0111

Description

Load one byte indirect from data space to register and toggles bits in the data space specified by the register. The instruction can only be used towards SRAM.

The Z-Pointer Register is left unchanged by the operation. This instruction is especially suited for changing status bits stored in SRAM.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	N/A
AVRxm	2
AVRxt	N/A
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack
LD Rd, Y	Rd = DS(Y)	0 <= d <= 31	PC = PC + 1	1000000ddddd1000	Y: Unchanged
LD Rd, Y+	Rd = DS(Y), Y = Y + 1	0 <= d <= 31	PC = PC + 1	1001000ddddd1001	Y: Post incremented
LD Rd, -Y	Y = Y - 1, Rd = DS(Y)	0 <= d <= 31	PC = PC + 1	1001000ddddd1010	Y: Pre decremented
LDD Rd, Y+q	Rd = DS(Y+q)	0 <= d <= 31, 0 <= q <= 63	PC = PC + 1	10q0qq0ddddd1qqq	Y: Unchanged, q: Displacement

Description

Loads one byte indirect with or without displacement from the data space to a register. The data space usually consists of the Register File, I/O memory and SRAM, refer to the device data sheet for a detailed definition of the data space.

The data location is pointed to by the Y (16-bit) Pointer Register in the Register File. Memory access is limited to the current data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the RAMPY in the register in the I/O area has to be changed.

The Y-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre- decremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the Y-Pointer Register. Note that only the low byte of the Y-pointer is updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPY Register in the I/O area is updated in parts with more than 64 KB data space or more than 64 KB program memory, and the increment/decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction are available on all devices.

In the Reduced Core AVRrc, the LD instruction can be used to achieve the same operation as LPM since the program memory is mapped to the data memory space.

The result of these combinations is undefined:

LD r28, Y+

LD r29, Y+

LD r28, -Y

LD r29, -Y

Using the Y-pointer:

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr   r29       ; Clear Y high byte
      ldi   r28,0x60  ; Set Y low byte to 0x60
      ld    r0,Y+     ; Load r0 with data space loc. 0x60(Y post inc)
      ld    r1,Y      ; Load r1 with data space loc. 0x61
      ldi   r28,0x63  ; Set Y low byte to 0x63
      ld    r2,Y      ; Load r2 with data space loc. 0x63
      ld    r3,-Y     ; Load r3 with data space loc. 0x62(Y pre dec)
      ldd   r4,Y+2    ; Load r4 with data space loc. 0x64

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii	iv
AVRe	2₍₁₎	2₍₁₎	2₍₁₎	2₍₁₎
AVRxm	2₍₁₎₍₃₎	2₍₁₎₍₃₎	3₍₁₎₍₃₎	3₍₁₎₍₃₎
AVRxt	2₍₂₎	2₍₂₎	2₍₂₎	2₍₂₎
AVRrc	1 / 2	2 / 3	2 / 3	N/A

Notes:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Cycle time for data memory access assumes internal RAM access, and are not valid for access to NVM. A minimum of one extra cycle must be added when accessing NVM. The additional time varies dependent on the NVM module implementation. See the NVMCTRL section in the specific devices data sheet for more information.

If the LD instruction is accessing I/O Registers, one cycle can be deducted.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack
LD Rd, Z	Rd = DS(Z)	0 <= d <= 31	PC = PC + 1	1000000ddddd0000	Z: Unchanged
LD Rd, Z+	Rd = DS(Z), Z = Z + 1	0 <= d <= 31	PC = PC + 1	1001000ddddd0001	Z: Post incremented
LD Rd, -Z	Z = Z - 1, Rd = DS(Z)	0 <= d <= 31	PC = PC + 1	1001000ddddd0010	Z: Pre decremented
LDD Rd, Z+q	Rd = DS(Z+q)	0 <= d <= 31, 0 <= q <= 63	PC = PC + 1	10q0qq0ddddd0qqq	Z: Unchanged, q: Displacement

Description

Loads one byte indirect with or without displacement from the data space to a register. The data space usually consists of the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.

The Z-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre- decremented. These features are especially suited for Stack Pointer usage of the Z-pointer Register. However, because the Z-Pointer Register can be used for indirect subroutine calls, indirect jumps, and table look-up, it is often more convenient to use the X- or Y-pointer as a dedicated Stack Pointer. Note that only the low byte of the Z-pointer is updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPZ Register in the I/O area is updated in parts with more than 64 KB data space or more than 64 KB program memory, and the increment/decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction are available on all devices.

In the Reduced Core AVRrc, the LD instruction can be used to achieve the same operation as LPM since the program memory is mapped to the data memory space.

For using the Z-pointer for table look-up in program memory, see the LPM and ELPM instructions.

The result of these combinations is undefined:

LD r30, Z+

LD r31, Z+

LD r30, -Z

LD r31, -Z

Using the Z-pointer:

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr   r31       ; Clear Z high byte
      ldi   r30,0x60  ; Set Z low byte to 0x60
      ld    r0,Z+     ; Load r0 with data space loc. 0x60(Z post inc)
      ld    r1,Z      ; Load r1 with data space loc. 0x61
      ldi   r30,0x63  ; Set Z low byte to 0x63
      ld    r2,Z      ; Load r2 with data space loc. 0x63
      ld    r3,-Z     ; Load r3 with data space loc. 0x62(Z pre dec)
      ldd   r4,Z+2    ; Load r4 with data space loc. 0x64

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii	iv
AVRe	2₍₁₎	2₍₁₎	2₍₁₎	2₍₁₎
AVRxm	2₍₁₎₍₃₎	2₍₁₎₍₃₎	3₍₁₎₍₃₎	3₍₁₎₍₃₎
AVRxt	2₍₂₎	2₍₂₎	2₍₂₎	2₍₂₎
AVRrc	1 / 2	2 / 3	2 / 3	N/A

Notes:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

If the LD instruction is accessing I/O Registers, one cycle can be deducted.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
LDI Rd,K	Rd = K	16 <= d <= 31, 0 <= K <= 255	PC = PC + 1	1110KKKKddddKKKK

Description

Loads an 8-bit constant directly to register 16 to 31.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr   r31       ; Clear Z high byte
      ldi   r30,0xF0  ; Set Z low byte to 0xF0
      lpm             ; Load constant from Program
                      ; memory pointed to by Z

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
LDS Rd,k	Rd = (k)	16 <= d <= 31, 0 <= k <= 127	PC = PC + 1	10100kkkddddkkkk

Description

Loads one byte from the data space to a register. The data space usually consists of the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.

A 7-bit address must be supplied. The address given in the instruction is coded to a data space address as follows:

ADDR[7:0] = (INST[8], INST[8], INST[10], INST[9], INST[3], INST[2], INST[1], INST[0])

Memory access is limited to the address range 0x40...0xbf.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      lds   r16,0x00  ; Load r16 with the contents of data space location 0x00
      add   r16,r17   ; add r17 to r16
      sts   0x00,r16  ; Write result to the same address it was fetched from

Words

1 (2 bytes)

Table Cycles

Name Note: Registers r0...r15 are remapped to r16...r31.	Cycles
AVRe	N/A
AVRxm	N/A
AVRxt	N/A
AVRrc	2

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
LDS Rd,k	Rd = DS(k)	0 <= d <= 31, 0 <= k <= 65535	PC = PC + 2	1001000ddddd0000kkkkkkkkkkkkkkkk

Description

A 16-bit address must be supplied. Memory access is limited to the current data segment of 64 KB. The LDS instruction uses the RAMPD Register to access memory above 64 KB. To access another data segment in devices with more than 64 KB data space, the RAMPD in the register in the I/O area has to be changed.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      lds   r2,0xFF00  ; Load r2 with the contents of data space location 0xFF00
      add   r2,r1      ; add r1 to r2
      sts   0xFF00,r2  ; Write back

Words

2 (4 bytes)

Table Cycles

Name	Cycles
AVRe	2₍₁₎
AVRxm	3₍₁₎₍₃₎
AVRxt	3₍₂₎
AVRrc	N/A

Notes:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

If the LD instruction is accessing I/O Registers, one cycle can be deducted.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack
LD Rd, X	Rd = DS(X)	0 <= d <= 31	PC = PC + 1	1001000ddddd1100	X: Unchanged
LD Rd, X+	Rd = DS(X) X = X + 1	0 <= d <= 31	PC = PC + 1	1001000ddddd1101	X: Post incremented
LD Rd, -X	X = X - 1 Rd = DS(X)	0 <= d <= 31	PC = PC + 1	1001000ddddd1110	X: Pre decremented

Description

Loads one byte indirect from the data space to a register. The data space usually consists of the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.

The data location is pointed to by the X (16-bit) Pointer Register in the Register File. Memory access is limited to the current data segment of 64 KB. To access another data segment in devices with more than 64 KB data space, the RAMPX in the register in the I/O area has to be changed.

The X-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre- decremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the X-Pointer Register. Note that only the low byte of the X-pointer is updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPX Register in the I/O area is updated in parts with more than 64 KB data space or more than 64 KB program memory, and the increment/decrement is added to the entire 24-bit address on such devices.

Not all variants of this instruction are available on all devices.

In the Reduced Core AVRrc, the LD instruction can be used to achieve the same operation as LPM since the program memory is mapped to the data memory space.

The result of these combinations is undefined:

LD r26, X+

LD r27, X+

LD r26, -X

LD r27, -X

Using the X-pointer:

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr   r27       ; Clear X high byte
      ldi   r26,0x60  ; Set X low byte to 0x60
      ld    r0,X+     ; Load r0 with data space loc. 0x60(X post inc)
      ld    r1,X      ; Load r1 with data space loc. 0x61
      ldi   r26,0x63  ; Set X low byte to 0x63
      ld    r2,X      ; Load r2 with data space loc. 0x63
      ld    r3,–X     ; Load r3 with data space loc. 0x62(X pre dec)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii
AVRe	2₍₁₎	2₍₁₎	2₍₁₎
AVRxm	2₍₁₎₍₃₎	2₍₁₎₍₃₎	3₍₁₎₍₃₎
AVRxt	2₍₂₎	2₍₂₎	2₍₂₎
AVRrc	1 / 2	2 / 3	2 / 3

Notes:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

If the LD instruction is accessing I/O Registers, one cycle can be deducted.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack
LPM	R0 = PS(Z)	None, R0 implied	PC = PC + 1	1001010111001000	Z: Unchanged, R0 implied destination register
LPM Rd, Z	Rd = PS(Z)	0 <= d <= 31	PC = PC + 1	1001000ddddd0100	Z: Unchanged
LPM Rd, Z+	Rd = PS(Z) Z = Z + 1	0 <= d <= 31	PC = PC + 1	1001000ddddd0101	Z: Post incremented

Description

Loads one byte pointed to by the Z-register into the destination register Rd. This instruction features a 100% space-effective constant initialization or constant data fetch. The program memory is organized in 16-bit words while the Z-pointer is a byte address. Thus, the least significant bit of the Z-pointer selects either low byte (ZLSb == 0) or

high byte (Z^LSb == 1). This instruction can address the first 64 KB (32K words) of program memory. The Z-Pointer

Register can either be left unchanged by the operation, or it can be incremented. The incrementation does not apply to the RAMPZ Register.

Devices with self-programming capability can use the LPM instruction to read the Fuse and Lock bit values. Refer to the device documentation for a detailed description.

The LPM instruction is not available on all devices. Refer to Appendix A.

The result of these combinations is undefined:

LPM r30, Z+

LPM r31, Z+

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      ldi   ZH, high(Table_1<<1)  ; Initialize Z-pointer
      ldi   ZL, low(Table_1<<1)
      lpm   r16, Z                ; Load constant from Program
                                  ; Memory pointed to by Z (r31:r30)
      ...
Table_1:
      dw    0x5876                ; 0x76 is addresses when Z_LSB == 0
                                  ; 0x58 is addresses when Z_LSB == 1
      ...

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	3
AVRxm	3
AVRxt	3
AVRrc	N/A

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

LSL Rd

C = Rd[7]

Rd = Rd << 1

0 <= d <= 31

PC = PC + 1

000011dddddddddd

C <-

b7 - - - - - - - - - - - - - - - - - - b0

Description

Shifts all bits in Rd one place to the left. Bit 0 is cleared. Bit 7 is loaded into the C flag of the SREG. This operation effectively multiplies signed and unsigned values by two.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	Rd3
S	⇔	N XOR V, for signed tests.
V	⇔	N XOR C, for N and C after the shift.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	Rd7	Set if, before the shift, the MSB of Rd was set; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

      add   r0,r4  ; Add r4 to r0
      lsl   r0     ; Multiply r0 by 2

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

LSR Rd

C = Rd[0]

Rd = Rd >> 1

0 <= d <= 31

PC = PC + 1

1001010ddddd0110

b7 - - - - - - - - - - - - - - - - - - b0

Description

Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is loaded into the C flag of the SREG. This operation effectively divides an unsigned value by two. The C flag can be used to round the result.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	⇔	N XOR C, for N and C after the shift.
N	0	0
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	Rd0	Set if, before the shift, the LSB of Rd was set; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

      add   r0,r4  ; Add r4 to r0
      lsr   r0     ; Divide r0 by 2

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
MOVW Rd,Rr	R[d+1]:Rd = R[r+1]:Rr	d ∈ {0,2,...,30}, r ∈ {0,2,...,30}	PC = PC + 1	00000001ddddrrrr

Description

This instruction makes a copy of one register pair into another register pair. The source register pair Rr+1:Rr is left unchanged, while the destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        movw  r17:16,r1:r0  ; Copy r1:r0 to r17:r16
        call  check         ; Call subroutine
        ...
check:  cpi   r16,0x11      ; Compare r16 to 0x11
        ...
        cpi   r17,0x32      ; Compare r17 to 0x32
        ...
        ret                 ; Return from subroutine

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
MOV Rd,Rr	Rd = Rr	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	001011rdddddrrrr

Description

This instruction makes a copy of one register into another. The source register Rr is left unchanged, while the destination register Rd is loaded with a copy of Rr.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

        mov   r16,r0    ; Copy r0 to r16
        call  check     ; Call subroutine
        ...
check:  cpi   r16,0x11  ; Compare r16 to 0x11
        ...
        ret             ; Return from subroutine

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
MULSU Rd,Rr	R1:R0 = Rd × Rr (signed = signed × unsigned)	16 <= d <= 23, 16 <= r <= 23	PC = PC + 1	000000110ddd0rrr

Description

This instruction performs 8-bit × 8-bit -> 16-bit multiplication of a signed and an unsigned number.

Product High

Product Low

Multiplicand

Multiplier

The multiplicand Rd and the multiplier Rr are two registers. The multiplicand Rd is a signed number, and the multiplier Rr is unsigned. The 16-bit signed product is placed in R1 (high byte) and R0 (low byte).

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	⇔	~R15 AND ~R14 AND ~R13 AND ~R12 AND ~R11 AND ~R10 AND ~R9 AND ~R8 ANDR7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x0000; cleared otherwise.
C	⇔	R15
R (Result)	R (Result) equals R1,R0 after the operation.

Example:

;******************************************************************************
;* DESCRIPTION
;* Signed multiply of two 16-bit numbers with 32-bit result.
;* USAGE
;* r19:r18:r17:r16 = r23:r22 * r21:r20
;******************************************************************************
muls16x16_32:
      clr   r2
      muls  r23, r21      ; (signed)ah * (signed)bh
      movw  r18, r0
      mul   r22, r20      ; al * bl
      movw  r16, r0
      mulsu r23, r20      ; (signed)ah * bl
      sbc   r19, r2
      add   r17, r0
      adc   r18, r1
      adc   r19, r2
      mulsu r21, r22      ; (signed)bh * al
      sbc   r19, r2
      add   r17, r0
      adc   r18, r1
      adc   r19, r2
      ret

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
MULS Rd,Rr	R1:R0 = Rd × Rr (signed = signed × signed)	16 <= d <= 31, 16 <= r <= 31	PC = PC + 1	00000010ddddrrrr

Description

This instruction performs 8-bit × 8-bit -> 16-bit signed multiplication.

Product High

Product Low

Multiplicand

Multiplier

The multiplicand Rd and the multiplier Rr are two registers containing signed numbers. The 16-bit signed product is placed in R1 (high byte) and R0 (low byte).

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	⇔	~R15 AND ~R14 AND ~R13 AND ~R12 AND ~R11 AND ~R10 AND ~R9 AND ~R8 ANDR7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x0000; cleared otherwise.
C	⇔	R15
R (Result)	R (Result) equals R1,R0 after the operation.

Example:

      muls  r21,r20  ; Multiply signed r21 and r20
      movw  r20,r0   ; Copy result back in r21:r20

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
MUL Rd,Rr	R1:R0 = Rd × Rr (unsigned = unsigned × unsigned)	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	100111rdddddrrrr

Description

This instruction performs 8-bit × 8-bit -> 16-bit unsigned multiplication.

Product High

Product Low

Multiplicand

Multiplier

The multiplicand Rd and the multiplier Rr are two registers containing unsigned numbers. The 16-bit unsigned product is placed in R1 (high byte) and R0 (low byte). Note that if the multiplicand or the multiplier is selected from R0 or R1, the result will overwrite those after multiplication.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	⇔	~R15 AND ~R14 AND ~R13 AND ~R12 AND ~R11 AND ~R10 AND ~R9 AND ~R8 ANDR7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x0000; cleared otherwise.
C	⇔	R15
R (Result)	R (Result) equals R1,R0 after the operation.

Example:

      mul   r5,r4   ; Multiply unsigned r5 and r4
      movw  r4,r0   ; Copy result back in r5:r4

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
NEG Rd	Rd = 0x00 - Rd	0 <= d <= 31	PC = PC + 1	1001010ddddd0001

Description

Replaces the contents of register Rd with its two's complement; the value 0x80 is left unchanged.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	R3 OR Rd3	Set if there was a borrow from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if there is a two's complement overflow from the implied subtraction from zero; cleared otherwise. A two's complement overflow will occur only if the contents of the Register after the operation (Result) is 0x80.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	R7 OR R6 OR R5 OR R4 OR R3 OR R2 OR R1 OR R0	Set if there is a borrow in the implied subtraction from zero; cleared otherwise. The C flag will be set in all cases except when the contents of the Register after the operation is 0x00.
R (Result)	R (Result) equals Rd after the operation.

Example:

      sub   r11,r0     ; Subtract r0 from r11
      brpl  positive   ; Branch if result positive
      neg   r11        ; Take two’s complement of r11
positive:
      nop              ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
NOP	No	None	PC = PC + 1	0000000000000000

Description

This instruction performs a single cycle No Operation.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr   r16       ; Clear r16
      ser   r17       ; Set r17
      out   0x18,r16  ; Write zeros to Port B
      nop             ; Wait (do nothing)
      out   0x18,r17  ; Write ones to Port B

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
ORI Rd,K	Rd = Rd OR K	16 <= d <= 31, 0 <= K <= 255	PC = PC + 1	0110KKKKddddKKKK

Description

Performs the logical OR between the contents of register Rd and a constant, and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	0	0	Cleared.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      ori   r16,0xF0   ; Set high nibble of r16
      ori   r17,1      ; Set bit 0 of r17

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
OR Rd,Rr	Rd = Rd OR Rr	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	001010rdddddrrrr

Description

Performs the logical OR between the contents of register Rd and register Rr, and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	0	0	Cleared.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      or    r15,r16   ; Do bitwise or between registers
      bst   r15,6     ; Store bit 6 of r15 in T bit
      brts  ok        ; Branch if T bit set
      ...
ok: 
      nop             ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
OUT A,Rr	I/O(A) = Rr	0 <= r <= 31, 0 <= A <= 63	PC = PC + 1	10111AArrrrrAAAA

Description

Stores data from register Rr in the Register File to I/O space.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr   r16       ; Clear r16
      ser   r17       ; Set r17
      out   0x18,r16  ; Write zeros to Port B
      nop             ; Wait (do nothing)
      out   0x18,r17  ; Write ones to Port B

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack:
POP Rd	Rd = STACK	0 <= d <= 31	PC = PC + 1	1001000ddddd1111		SP = SP + 1

Description

This instruction loads register Rd with a byte from the STACK. The Stack Pointer is pre-incremented by 1 before the POP.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      call  routine  ; Call subroutine
      ...
routine: 
      push  r14      ; Save r14 on the Stack
      push  r13      ; Save r13 on the Stack
      ...
      pop   r13      ; Restore r13
      pop   r14      ; Restore r14
      ret            ; Return from subroutine

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2₍₁₎
AVRxt	2
AVRrc	3

Note:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack:
PUSH Rr	STACK = Rr	0 <= r <= 31	PC = PC + 1	1001001ddddd1111		SP = SP - 1

Description

This instruction stores the contents of register Rr on the STACK. The Stack Pointer is post-decremented by 1 after the PUSH.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      call  routine  ; Call subroutine
      ...
routine: 
      push  r14      ; Save r14 on the Stack
      push  r13      ; Save r13 on the Stack
      ...
      pop   r13      ; Restore r13
      pop   r14      ; Restore r14
      ret            ; Return from subroutine

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	1₍₁₎
AVRxt	1
AVRrc	1

Note:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment:

Stack:

RCALL k

PC = PC + k + 1

-2K <= k < 2K

PC = PC + k + 1

1101kkkkkkkkkkkk

Devices with 16-bit PC, 128 KB program memory maximum.

STACK = PC + 1

SP = SP - 2 (2 bytes, 16 bits)

RCALL k

PC = PC + k + 1

-2K <= k < 2K

PC = PC + k + 1

1101kkkkkkkkkkkk

Devices with 22-bit PC, 8 MB program memory maximum.

STACK = PC + 1

SP = SP - 3 (3 bytes, 22 bits)

Description

Relative call to an address within PC - 2K + 1 and PC + 2K (words). The return address (the instruction after the RCALL) is stored onto the Stack. See also CALL. For AVR microcontrollers with program memory not exceeding 4K words (8 KB), this instruction can address the entire memory from every address location. The Stack Pointer uses a post-decrement scheme during RCALL.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      rcall routine  ; Call subroutine
      ...
routine: 
      push  r14      ; Save r14 on the Stack
      ...
      pop   r14      ; Restore r14
      ret            ; Return from subroutine

Words

1 (2 bytes)

Table Cycles

Name	Cycles 9/16-bit PC	22-bit PC
AVRe	3₍₁₎	4₍₁₎
AVRxm	2₍₁₎	3₍₁₎
AVRxt	2	3
AVRrc	3	N/A

Note:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack:
RETI	PC(15:0) = STACK	None	See Operation	1001010100011000	Devices with 16-bit PC, 128 KB program memory maximum.	SP = SP + 2 (2 bytes, 16 bits)
RETI	PC(21:0) = STACK	None	See Operation	1001010100011000	Devices with 22-bit PC, 8 MB program memory maximum.	SP = SP + 3 (3 bytes, 22 bits)

Description

Returns from the interrupt. The return address is loaded from the STACK, and the Global Interrupt Enable bit is set.

Note that the Status Register is not automatically stored when entering an interrupt routine, and it is not restored when returning from an interrupt routine. This must be handled by the application program. The Stack Pointer uses a pre-increment scheme during RETI.

Status Register (SREG) and Boolean Formula

I	1	1	The I flag is set.
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      ... 
extint:
      push  r0  ; Save r0 on the Stack
      ...
      pop   r0  ; Restore r0
      reti      ; Return and enable interrupts

Words

1 (2 bytes)

Table Cycles

Name	Cycles 9/16-bit PC	22-bit PC
AVRe	4₍₂₎	5₍₂₎
AVRxm	4₍₂₎	5₍₂₎
AVRxt	4	5
AVRrc	6	N/A

Notes:

RETI behaves differently in AVRe, AVRxm, and AVRxt devices. In the AVRe series of devices, the Global Interrupt Enable bit is cleared by hardware once an interrupt occurs, and this bit is set when RETI is executed. In the AVRxm and AVRxt devices, RETI will not modify the Global Interrupt Enable bit in SREG since it is not cleared by hardware while entering ISR. This bit should be modified using SEI and CLI instructions when needed.

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack:
RET	PC(15:0) = STACK	None	See Operation	1001010100001000	Devices with 16-bit PC, 128 KB program memory maximum.	SP = SP + 2, (2 bytes,16 bits)
RET	PC(21:0) = STACK	None	See Operation	1001010100001000	Devices with 22-bit PC, 8 MB program memory maximum.	SP = SP + 3, (3 bytes,22 bits)

Description

Returns from the subroutine. The return address is loaded from the STACK. The Stack Pointer uses a pre-increment scheme during RET.

Operation:

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      call  routine  ; Call subroutine
      ...
routine: 
      push  r14      ; Save r14 on the Stack
      ...
      pop   r14      ; Restore r14
      ret            ; Return from subroutine

Words

1 (2 bytes)

Table Cycles

Name	Cycles 9/16-bit PC	22-bit PC
AVRe	4₍₁₎	5₍₁₎
AVRxm	4₍₁₎	5₍₁₎
AVRxt	4	5
AVRrc	6	N/A

Note:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack:
RJMP	PC = PC + k + 1	k -2K <= k < 2K	PC = PC + k + 1	1100kkkkkkkkkkkk		Unchanged

Description

Relative jump to an address within PC - 2K +1 and PC + 2K (words). For AVR microcontrollers with pogram memory not exceeding 4K words (8 KB), this instruction can address the entire memory from every address location. See also JMP.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      cpi   r16,0x42  ; Compare r16 to 0x42
      brne  error     ; Branch if r16 <> 0x42
      rjmp  ok        ; Unconditional branch
error:
      add   r16,r17   ; Add r17 to r16
      inc   r16       ; Increment r16
ok: 
      nop             ; Destination for rjmp (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	2

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
ROL Rd	C:Rd = ROL(Rd:C)	0 <= d <= 31	PC = PC + 1	000111dddddddddd

Description

Shifts all bits in Rd one place to the left. The C flag is shifted into bit 0 of Rd. Bit 7 is shifted into the C flag. This operation, combined with LSL, effectively multiplies multi-byte signed and unsigned values by two.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	Rd3
S	⇔	N XOR V, for signed tests.
V	⇔	N XOR C, for N and C after the shift.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	Rd7	Set if, before the shift, the MSB of Rd was set; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

      lsl   r18     ; Multiply r19:r18 by two
      rol   r19     ; r19:r18 is a signed or unsigned two-byte integer
      brcs  oneenc  ; Branch if carry set
      ...
oneenc: 
      nop           ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
ROR Rd	Rd:C = ROR(C:Rd)	0 <= d <= 31	PC = PC + 1	1001010ddddd0111

Description

Shifts all bits in Rd one place to the right. The C flag is shifted into bit 7 of Rd. Bit 0 is shifted into the C flag. This operation, combined with ASR, effectively divides multi-byte signed values by two. Combined with LSR, it effectively divides multi-byte unsigned values by two. The Carry flag can be used to round the result.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	⇔	N XOR C, for N and C after the shift.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	Rd0	Set if, before the shift, the LSB of Rd was set; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

      lsr   r19       ; Divide r19:r18 by two
      ror   r18       ; r19:r18 is an unsigned two-byte integer
      brcc  zeroenc1  ; Branch if carry cleared
      asr   r17       ; Divide r17:r16 by two
      ror   r16       ; r17:r16 is a signed two-byte integer
      brcc  zeroenc2  ; Branch if carry cleared
      ...
zeroenc1: 
      nop             ; Branch destination (do nothing)
      ...
zeroenc1: 
      nop             ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SBCI Rd,K	Rd = Rd - K - C	16 <= d <= 31, 0 <= K <= 255	PC = PC + 1	0100KKKKddddKKKK

Description

Subtracts a constant from a register and subtracts with the C flag, and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	~Rd3 AND K3 OR K3 AND R3 OR R3 AND ~Rd3	Set if there was a borrow from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	Rd7 AND ~K7 AND ~R7 OR ~Rd7 AND K7 AND R7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0 AND Z	The previous value remains unchanged when the result is zero; cleared otherwise.
C	⇔	~Rd7 AND K7 OR K7 AND R7 OR R7 AND ~Rd7	Set if the absolute value of the constant plus previous carry is larger than the absolute value of Rd; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

                          ; Subtract 0x4F23 from r17:r16
      subi  r16,0x23      ; Subtract low byte
      sbci  r17,0x4F      ; Subtract with carry high byte

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SBC Rd,Rr	Rd = Rd - Rr - C	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	000010rdddddrrrr

Description

Subtracts two registers and subtracts with the C flag, and places the result in the destination register Rd.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	⇔	~Rd3 AND Rr3 OR Rr3 AND R3 OR R3 AND ~Rd3	Set if there was a borrow from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	Rd7 AND ~Rr7 AND ~R7 OR ~Rd7 AND Rr7 AND R7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0 AND Z	The previous value remains unchanged when the result is zero; cleared otherwise.
C	⇔	~Rd7 AND Rr7 OR Rr7 AND R7 OR R7 AND ~Rd7	Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of the Rd; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

                        ; Subtract r1:r0 from r3:r2
      sub   r2,r0       ; Subtract low byte
      sbc   r3,r1       ; Subtract with carry high byte

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

SBIC A,b

If I/O(A,b) == 0 then PC = PC + 2 (or 3) else PC = PC + 1

0 <= A <= 31, 0 <= b <= 7

PC = PC + 1, Condition false - no skip

PC = PC + 2, Skip a one word instruction

PC = PC + 3, Skip a two word instruction

10011001AAAAAbbb

Description

This instruction tests a single bit in an I/O Register and skips the next instruction if the bit is cleared. This instruction operates on the lower 32 I/O Registers - addresses 0-31.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

wait:
      sbic  0x1C,1    ; Skip next instruction if 0x1C bit 1 is cleared
      rjmp  wait      ; Bit not cleared yet
      nop             ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii
AVRe	1	2	3
AVRxm	2	3	4
AVRxt	1	2	3
AVRrc	1	2	N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

SBIS A,b

If I/O(A,b) == 1 then PC = PC + 2 (or 3) else PC = PC + 1

0 <= A <= 31, 0 <= b <= 7

PC = PC + 1, Condition false - no skip

PC = PC + 2, Skip a one word instruction

PC = PC + 3, Skip a two word instruction

10011011AAAAAbbb

Description

This instruction tests a single bit in an I/O Register and skips the next instruction if the bit is set. This instruction operates on the lower 32 I/O Registers - addresses 0-31.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

waitset: 
      sbis  0x10,0   ; Skip next instruction if bit 0 at 0x10 is set
      rjmp  waitset  ; Bit not set
      nop            ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii
AVRe	1	2	3
AVRxm	2	3	4
AVRxt	1	2	3
AVRrc	1	2	N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SBIW Rd,K	R[d+1]:Rd = R[d+1]:Rd - K	d ∈ {24,26,28,30}, 0 <= K <= 63	PC = PC + 1	10010111KKddKKKK

Description

Subtracts an immediate value (0-63) from a register pair and places the result in the register pair. This instruction operates on the upper four register pairs and is well suited for operations on the Pointer Registers.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	⇔	~R15 AND Rdh7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R15	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R15 AND ~R14 AND ~R13 AND ~R12 AND ~R11 AND ~R10 AND ~R9 AND ~R8 ANDR7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x0000; cleared otherwise.
C	⇔	R15 AND ~Rdh7	Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.
R (Result)	R (Result) equals R[d+1]:Rd after the operation.

Example:

      sbiw  r24,1   ; Subtract 1 from r25:r24
      sbiw  YL,63   ; Subtract 63 from the Y-pointer(r29:r28)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	2
AVRxt	2
AVRrc	N/A

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SBI A,b	I/O(A,b) = 1	0 <= A <= 31, 0 <= b <= 7	PC = PC + 1	10011010AAAAAbbb

Description

Sets a specified bit in an I/O Register. This instruction operates on the lower 32 I/O Registers - addresses 0-31.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      sbi   0x1C,0   ; Set bit 0 at address 0x1C

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	2
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

SBRC Rr,b

If Rr(b) == 0 then PC = PC + 2 (or 3) else PC = PC + 1

0 <= r <= 31, 0 <= b <= 7

PC = PC + 1, Condition false - no skip

PC = PC + 2, Skip a one word instruction

PC = PC + 3, Skip a two word instruction

1111110rrrrr0bbb

Description

This instruction tests a single bit in a register and skips the next instruction if the bit is cleared.

Operation:

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      sub   r0,r1  ; Subtract r1 from r0
      sbrc  r0,7   ; Skip if bit 7 in r0 cleared
      sub   r0,r1  ; Only executed if bit 7 in r0 not cleared
      nop          ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii
AVRe	1	2	3
AVRxm	1	2	3
AVRxt	1	2	3
AVRrc	1	2	N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

SBRC Rr,b

If Rr(b) == 0 then PC = PC + 2 (or 3) else PC = PC + 1

0 <= r <= 31, 0 <= b <= 7

PC = PC + 1, Condition false - no skip

PC = PC + 2, Skip a one word instruction

PC = PC + 3, Skip a two word instruction

1111110rrrrr0bbb

Description

This instruction tests a single bit in a register and skips the next instruction if the bit is cleared.

Operation:

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      sub   r0,r1  ; Subtract r1 from r0
      sbrc  r0,7   ; Skip if bit 7 in r0 cleared
      sub   r0,r1  ; Only executed if bit 7 in r0 not cleared
      nop          ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii
AVRe	1	2	3
AVRxm	1	2	3
AVRxt	1	2	3
AVRrc	1	2	N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

SBRS Rr,b

If Rr(b) == 1 then PC = PC + 2 (or 3) else PC = PC + 1

0 <= r <= 31, 0 <= b <= 7

PC = PC + 1, Condition false - no skip

PC = PC + 2, Skip a one word instruction

PC = PC + 3, Skip a two word instruction

1111111rrrrr0bbb

Description

This instruction tests a single bit in a register and skips the next instruction if the bit is set.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      sub   r0,r1  ; Subtract r1 from r0
      sbrs  r0,7   ; Skip if bit 7 in r0 set
      neg   r0     ; Only executed if bit 7 in r0 not set
      nop          ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii
AVRe	1	2	3
AVRxm	1	2	3
AVRxt	1	2	3
AVRrc	1	2	N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

Operations:

Syntax:

Operation:

Operands:

Program Counter:

Opcode

Comment

Stack

SBRS Rr,b

If Rr(b) == 1 then PC = PC + 2 (or 3) else PC = PC + 1

0 <= r <= 31, 0 <= b <= 7

PC = PC + 1, Condition false - no skip

PC = PC + 2, Skip a one word instruction

PC = PC + 3, Skip a two word instruction

1111111rrrrr0bbb

Description

This instruction tests a single bit in a register and skips the next instruction if the bit is set.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      sub   r0,r1  ; Subtract r1 from r0
      sbrs  r0,7   ; Skip if bit 7 in r0 set
      neg   r0     ; Only executed if bit 7 in r0 not set
      nop          ; Continue (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles i	ii	iii
AVRe	1	2	3
AVRxm	1	2	3
AVRxt	1	2	3
AVRrc	1	2	N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SBR Rd,K	Rd = Rd OR K	16 <= d <= 31, 0 <= K <= 255	PC = PC + 1	Equivalent to ORI Rd,K.

Description

Sets specified bits in register Rd. Performs the logical ORI between the contents of register Rd and a constant mask K, and places the result in the destination register Rd. (Equivalent to ORI Rd,K.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	0	0	Cleared.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      sbr   r16,3     ; Set bits 0 and 1 in r16
      sbr   r17,0xF0  ; Set 4 MSB in r17

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SEC	C = 1	None	PC = PC + 1	1001010000001000

Description

Sets the Carry (C) flag in SREG (Status Register). (Equivalent to instruction BSET 0.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	1	1	Carry flag set.

Example:

      sec         ; Set Carry flag
      adc  r0,r1  ; r0=r0+r1+1

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SEH	H = 1	None	PC = PC + 1	1001010001011000

Description

Sets the Half Carry (H) flag in SREG (Status Register). (Equivalent to instruction BSET 5.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	1	1	Half Carry flag set.
S	–
V	–
N	–
Z	–
C	–

Example:

      seh  ; Set Half Carry flag

Words

1 (2 bytes)

Table Cycles

Name

...........continued

Name

AVRxm

AVRxt

AVRrc

Cycles

AVRe

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SEI	I = 1	None	PC = PC + 1	1001010001111000

Description

Sets the Global Interrupt Enable (I) bit in SREG (Status Register). The instruction following SEI will be executed before any pending interrupts.

Status Register (SREG) and Boolean Formula

I	1	1	Global Interrupt Enable bit set.
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      sei      ; set global interrupt enable
      sleep    ; enter sleep, waiting for interrupt
               ; note: will enter sleep before any pending interrupt(s)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SEN	N = 1	None	PC = PC + 1	1001010000101000

Description

Sets the Negative (N) flag in SREG (Status Register). (Equivalent to instruction BSET 2.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	1	1	Negative flag set.
Z	–
C	–

Example:

      add   r2,r19  ; Add r19 to r2
      sen           ; Set Negative flag

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SER Rd	Rd = 0xFF	16 <= d <= 31	PC = PC + 1	11101111dddd1111

Description

Loads 0xFF directly to register Rd. (Equivalent to instruction LDI Rd,0xFF).

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr  r16       ; Clear r16
      ser  r17       ; Set r17
      out  0x18,r16  ; Write zeros to Port B
      nop            ; Delay (do nothing)
      out  0x18,r17  ; Write ones to Port B

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SES	S = 1	None	PC = PC + 1	1001010001001000

Description

Sets the Sign (S) flag in SREG (Status Register). (Equivalent to instruction BSET 4.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	1	1	Sign flag set.
V	–
N	–
Z	–
C	–

Example:

      add   r2,r19  ; Add r19 to r2
      ses           ; Set Negative flag

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SET	T = 1	None	PC = PC + 1	1001010001101000

Description

Sets the T bit in SREG (Status Register). (Equivalent to instruction BSET 6.)

Status Register (SREG) and Boolean Formula

I	–
T	1	1	T bit set.
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      set  ; Set T bit

Words

1 (2 bytes)

Table Cycles

Name

...........continued

Name

AVRxm

AVRxt

AVRrc

Cycles

AVRe

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SEV	V = 1	None	PC = PC + 1	1001010000111000

Description

Sets the Overflow (V) flag in SREG (Status Register). (Equivalent to instruction BSET 3.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	1	V: 1	Overflow flag set.
N	–
Z	–
C	–

Example:

      add   r2,r19  ; Add r19 to r2
      sev           ; Set Overflow flag

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SEZ	Z = 1	None	PC = PC + 1	1001010000011000

Description

Sets the Zero (Z) flag in SREG (Status Register). (Equivalent to instruction BSET 1.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	1	1	Zero flag set.
C	–

Example:

      add   r2,r19  ; Add r19 to r2
      sez           ; Set Zero flag

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SLEEP	Refer to the device documentation for a detailed description of SLEEP usage.	None	PC = PC + 1	1001010110001000

Description

This instruction sets the circuit in sleep mode defined by the MCU Control Register.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      mov   r0,r11       ; Copy r11 to r0
      ldi   r16,(1<<SE)  ; Enable sleep mode
      out   MCUCR, r16
      sleep              ; Put MCU in sleep mode

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SPM	PS(RAMPZ:Z) = 0xffff	None	PC = PC + 1	1001010111101000	Erase program memory page
SPM	PS(RAMPZ:Z) = R1:R0	None	PC = PC + 1	1001010111101000	Write program memory word
SPM	PS(RAMPZ:Z) = R1:R0	None	PC = PC + 1	1001010111101000	Load page buffer
SPM	PS(RAMPZ:Z) = BUFFER	None	PC = PC + 1	1001010111101000	Write page buffer to program memory
SPM	BLBITS = R1:R0	None	PC = PC + 1	1001010111101000	Set Boot Loader Lock bits

Description

SPM can be used to erase a page in the program memory, to write a page in the program memory (that is already erased), and to set Boot Loader Lock bits. In some devices, the Program memory can be written one word at a time. In other devices, an entire page can be programmed simultaneously after first filling a temporary page buffer. In all cases, the program memory must be erased one page at a time. When erasing the program memory, the RAMPZ and Z-register are used as page address. When writing the program memory, the RAMPZ and Z-register are used as page or word address, and the R1:R0 register pair is used as data(1). The Flash is word-accessed for code space write operations, so the least significant bit of the RAMPZ register concatenated with the Z register should

be set to ‘0'. When setting the Boot Loader Lock bits, the R1:R0 register pair is used as data. Refer to the device documentation for the detailed description of SPM usage. This instruction can address the entire program memory.

The SPM instruction is not available on all devices. Refer to Appendix A.

Note: 1. R1 determines the instruction high byte, and R0 determines the instruction low byte.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

 ; This example shows SPM write of one page for devices with page write
 ; - the routine writes one page of data from RAM to Flash
 ;   the first data location in RAM is pointed to by the Y-pointer
 ;   the first data location in Flash is pointed to by the Z-pointer
 ; - error handling is not included
 ; - the routine must be placed inside the boot space
 ;   (at least the do_spm sub routine)
 ; - registers used: r0, r1, temp1, temp2, looplo, loophi, spmcrval
 ; (temp1, temp2, looplo, loophi, spmcrval must be defined by the user)
 ; storing and restoring of registers is not included in the routine
 ; register usage can be optimized at the expense of code size
         equ   PAGESIZEB = PAGESIZE*2       ; PAGESIZEB is page size in BYTES, not words
        org   SMALLBOOTSTART
 write_page:
                                           ; page erase
        ldi   spmcrval, (1<<PGERS) + (1<<SPMEN)
        call  do_spm
                                           ; transfer data from RAM to Flash page buffer
        ldi   looplo, low(PAGESIZEB)       ; init loop variable
        ldi   loophi, high(PAGESIZEB)      ; not required for PAGESIZEB<=256
 wrloop: 
        ld    r0, Y+
        ld    r1, Y+
        ldi   spmcrval, (1<<SPMEN)
        call  do_spm
        adiw  ZL, 2
        sbiw  looplo, 2                    ; use subi for PAGESIZEB<=256
        brne  wrloop
                                           ; execute page write
        subi  ZL, low(PAGESIZEB)           ; restore pointer
        sbci  ZH, high(PAGESIZEB)          ; not required for PAGESIZEB<=256
        ldi   spmcrval, (1<<PGWRT) + (1<<SPMEN)
        call  do_spm
                                            ; read back and check, optional
        ldi   looplo, low(PAGESIZEB)       ; init loop variable
        ldi   loophi, high(PAGESIZEB)      ; not required for PAGESIZEB<=256
        subi  YL, low(PAGESIZEB)           ; restore pointer
        sbci  YH, high(PAGESIZEB)
 rdloop: 
        lpm   r0, Z+
        ld    r1, Y+
        cpse  r0, r1
        jmp   error
        sbiw  looplo, 2                    ; use subi for PAGESIZEB<=256
        brne  rdloop
         ret                                ; return
do_spm:
        in    temp2, SREG                  ; input: spmcrval determines SPM action
        cli                                ; disable interrupts if enabled, store status
 wait:
        in    temp1, SPMCR                 ; check for previous SPM complete
        sbrc  temp1, SPMEN
        rjmp  wait
         out   SPMCR, spmcrval              ; SPM timed sequence
        spm
         out   SREG, temp2                  ; restore SREG (to enable interrupts if 
                                           ; originally enabled)
        ret

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	-₍₁₎
AVRxm	N/A
AVRxt	N/A
AVRrc	N/A

Note:

Varies with the programming time of the device.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SPM	PS(RAMPZ:Z) = 0xffff	None	PC = PC + 1	1001010111101000	Erase program memory page
SPM	PS(RAMPZ:Z) = R1:R0	None	PC = PC + 1	1001010111101000	Write to program memory word₍₁₎
SPM	PS(RAMPZ:Z) = R1:R0	None	PC = PC + 1	1001010111101000	Load Page Buffer₍₂₎
SPM	PS(RAMPZ:Z) = BUFFER	None	PC = PC + 1	1001010111101000	Write Page Buffer to program memory₍₂₎
SPM Z+	PS(RAMPZ:Z) = 0xfff, Z = Z + 2	None	PC = PC + 1	1001010111111000	Erase program memory page, Z post incremented
SPM Z+	PS(RAMPZ:Z) = R1:R0, Z = Z + 2	None	PC = PC + 1	1001010111111000	Write to program memory word, Z post incremented₍₁₎
SPM Z+	PS(RAMPZ:Z) = R1:R0, Z = Z + 2	None	PC = PC + 1	1001010111111000	Load Page Buffer, Z post incremented₍₂₎
SPM Z+	PS(RAMPZ:Z) =BUFFER, Z = Z + 2	None	PC = PC + 1	1001010111111000	Write Page Buffer to program memory, Z post incremented⁽²⁾

Description

SPM can be used to erase a page in the program memory and to write a page in the program memory (that is already erased). In some devices, the program memory can be written one word at a time. In other devices, an entire page can be programmed simultaneously after first filling a temporary page buffer. In all cases, the program memory must be erased one page at a time. When erasing the program memory, the RAMPZ and Z-register are used as page address. When writing the program memory, the RAMPZ and Z-register are used as page or word address, and the R1:R0 register pair is used as data(1). The Flash is word-accessed for code space write operations, so the least

significant bit of the RAMPZ register concatenated with the Z register should be set to ‘0'.

Refer to the device documentation for a detailed description of SPM usage. This instruction can address the entire program memory.

The SPM instruction is not available on all devices. Refer to Appendix A.

Note: 1. R1 determines the instruction high byte, and R0 determines the instruction low byte.

Notes:

Not all devices can write directly to program memory, see device data sheet for detailed description of SPM usage.

Not all devices have a page buffer, see device data sheet for detailed description of SPM usage.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Words

1 (2 bytes)

Table Cycles

Name	Cycles i-iv	v-viii
AVRe	N/A	N/A
AVRxm	-₍₁₎	-₍₁₎
AVRxt	-₍₁₎	-₍₁₎
AVRrc	N/A	N/A

Note:

Varies with the programming time of the device.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack
ST Y, Rr	DS(Y) = Rr	0 <= r <= 31	PC = PC + 1	1000001rrrrr1000	Y: Unchanged
ST Y+, Rr	DS(Y) = Rr, Y = Y+1	0 <= r <= 31	PC = PC + 1	1001001rrrrr1001	Y: Post incremented
ST -Y, Rr	Y = Y - 1, DS(Y) = Rr	0 <= r <= 31	PC = PC + 1	1001001rrrrr1010	Y: Pre decremented
STD Y+q, Rr	DS(Y+q) = Rr	0 <= r <= 31, 0 <= q <= 63	PC = PC + 1	10q0qq1rrrrr1qqq	Y: Unchanged, q: Displacement

Description

Stores one byte indirect with or without displacement from a register to data space. The data space usually consists of the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.

The Y-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre- decremented. These features are especially suited for accessing arrays, tables, and Stack Pointer usage of the Y-Pointer Register. Note that only the low byte of the Y-pointer is updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPY Register in the I/O area is updated in parts with more than 64 KB data space or more than 64 KB program memory, and the increment/ decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction are available on all devices.

The result of these combinations is undefined:

ST Y+, r28

ST Y+, r29

ST -Y, r28

ST -Y, r29

Using the Y-pointer:

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr   r29       ; Clear Y high byte
      ldi   r28,0x60  ; Set Y low byte to 0x60
      st    Y+,r0     ; Store r0 in data space loc. 0x60(Y post inc)
      st    Y,r1      ; Store r1 in data space loc. 0x61
      ldi   r28,0x63  ; Set Y low byte to 0x63
      st    Y,r2      ; Store r2 in data space loc. 0x63
      st    -Y,r3     ; Store r3 in data space loc. 0x62(Y pre dec)
      std   Y+2,r4    ; Store r4 in data space loc. 0x64

Words

1 (2 bytes)

Table Cycles

Name	Cycles (i)	(ii)	(iii)	(iv)
AVRe	2₍₁₎	2₍₁₎	2₍₁₎	2₍₁₎
AVRxm	1₍₁₎	1₍₁₎	2₍₁₎	2₍₁₎
AVRxt	1₍₂₎	1₍₂₎	1₍₂₎	1₍₂₎
AVRrc	1	1	2	N/A

Notes:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack
ST Z, Rr	DS(Z) =Rr	0 <= r <= 31	PC = PC + 1	1000001rrrrr0000	Z: Unchanged
ST Z+, Rr	DS(Z) = Rr, Z = Z+1	0 <= r <= 31	PC = PC + 1	1001001rrrrr0001	Z: Post incremented
ST -Z, Rr	Z = Z - 1, DS(Z) = Rr	0 <= r <= 31	PC = PC + 1	1001001rrrrr0010	Z: Pre decremented
STD Z+q, Rr	DS(Z+q) = Rr	0 <= r <= 31, 0 <= q <= 63	PC = PC + 1	10q0qq1rrrrr0qqq	Z: Unchanged, q: Displacement

Description

The Z-Pointer Register can either be left unchanged by the operation, or it can be post-incremented or pre- decremented. These features are especially suited for Stack Pointer usage of the Z-Pointer Register. However, because the Z-Pointer Register can be used for indirect subroutine calls, indirect jumps, and table look-up, it is often more convenient to use the X- or Y-pointer as a dedicated Stack Pointer. Note that only the low byte of the Z-pointer is updated in devices with no more than 256 bytes of data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPZ Register in the I/O area is updated in parts with more than 64 KB data space or more than 64 KB program memory, and the increment/decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction are available on all devices.

The result of these combinations is undefined:

ST Z+, r30

ST Z+, r31

ST -Z, r30

ST -Z, r31

Using the Z-pointer:

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr   r31       ; Clear Z high byte
      ldi   r30,0x60  ; Set Z low byte to 0x60
      st    Z+,r0     ; Store r0 in data space loc. 0x60(Z post inc)
      st    Z,r1      ; Store r1 in data space loc. 0x61
      ldi   r30,0x63  ; Set Z low byte to 0x63
      st    Z,r2      ; Store r2 in data space loc. 0x63
      st    -Z,r3     ; Store r3 in data space loc. 0x62(Z pre dec)
      std   Z+2,r4    ; Store r4 in data space loc. 0x64

Words

1 (2 bytes)

Table Cycles

Name	Cycles (i)	(ii)	(iii)	(iv)
AVRe	2₍₁₎	2₍₁₎	2₍₁₎	2₍₁₎
AVRxm	1₍₁₎	1₍₁₎	2₍₁₎	2₍₁₎
AVRxt	1₍₂₎	1₍₂₎	1₍₂₎	1₍₂₎
AVRrc	1	1	2	N/A

Notes:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
STS k,Rr	(k) = Rr	16 <= r <= 31, 0 <= k <= 127	PC = PC + 1	10101kkkddddkkkk

Description

Stores one byte from a Register to the data space. The data space usually consists of the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.

A 7-bit address must be supplied. The address given in the instruction is coded to a data space address as follows:

ADDR[7:0] = (INST[8], INST[8], INST[10], INST[9], INST[3], INST[2], INST[1], INST[0])

Memory access is limited to the address range 0x40...0xbf of the data segment.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      lds   r16,0x00  ; Load r16 with the contents of data space location 0x00
      add   r16,r17   ; add r17 to r16
      sts   0x00,r16  ; Write result to the same address it was fetched from

Words

1 (2 bytes)

Table Cycles

Name Note: Registers r0...r15 are remapped to r16...r31.	Cycles
AVRe	N/A
AVRxm	N/A
AVRxt	N/A
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
STS k,Rr	DS(k) = Rr	0 <= r <= 31, 0 <= k <= 65535	PC = PC + 2	1001001ddddd0000kkkkkkkkkkkkkkkk

Description

A 16-bit address must be supplied. Memory access is limited to the current data segment of 64 KB. The STS instruction uses the RAMPD Register to access memory above 64 KB. To access another data segment in devices with more than 64 KB data space, the RAMPD in the register in the I/O area has to be changed.

This instruction is not available on all devices. Refer to Appendix A.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      lds   r2,0xFF00    ; Load r2 with the contents of data space location 0xFF00
      add   r2,r1        ; add r1 to r2
      sts   0xFF00,r2    ; Write back

Words

2 (4 bytes)

Table Cycles

Name	Cycles
AVRe	2₍₁₎
AVRxm	2₍₁₎
AVRxt	2₍₂₎
AVRrc	N/A

Notes:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment:	Stack
ST X, Rr	DS(X) = Rr	0 <= r <= 31	PC = PC + 1	1001001rrrrr1100	X: Unchanged
ST X+, Rr	DS(X) = Rr, X = X+1	0 <= r <= 31	PC = PC + 1	1001001rrrrr1101	X: Post incremented
ST -X, Rr	X = X - 1, DS(X) = Rr	0 <= r <= 31	PC = PC + 1	1001001rrrrr1110	X: Pre decremented

Description

Stores one byte indirect from a register to data space. The data space usually consists of the Register File, I/O memory, and SRAM, refer to the device data sheet for a detailed definition of the data space.

purposes. The RAMPX Register in the I/O area is updated in parts with more than 64 KB data space or more than 64 KB program memory, and the increment/ decrement is added to the entire 24-bit address on such devices.

Not all variants of this instruction are available on all devices.

The result of these combinations is undefined:

ST X+, r26

ST X+, r27

ST -X, r26

ST -X, r27

Using the X-pointer:

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      clr   r27        ; Clear X high byte
      ldi   r26,0x60   ; Set X low byte to 0x60
      st    X+,r0      ; Store r0 in data space loc. 0x60(X post inc)
      st    X,r1       ; Store r1 in data space loc. 0x61
      ldi   r26,0x63   ; Set X low byte to 0x63
      st    X,r2       ; Store r2 in data space loc. 0x63
      st    -X,r3      ; Store r3 in data space loc. 0x62(X pre dec)

Words

1 (2 bytes)

Table Cycles

Name	Cycles (i)	(ii)	(iii)
AVRxm	1₍₁₎	1₍₁₎	1₍₂₎
AVRxt	1₍₂₎	1₍₂₎	1₍₂₎
AVRrc	1	1	2
AVRe	2₍₁₎	2₍₁₎	2₍₁₎

Notes:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SUBI Rd,K	Rd = Rd - K	16 <= d <= 31, 0 <= K <= 255	PC = PC + 1	0101KKKKddddKKKK

Description

Subtracts a register and a constant, and places the result in the destination register Rd. This instruction is working on Register R16 to R31 and is very well suited for operations on the X, Y, and Z-pointers.

Status Register and Boolean Formula

I	–
T	–
H	⇔	~Rd3 AND K3 OR K3 AND R3 OR R3 AND ~Rd3	Set if there was a borrow from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	Rd7 AND ~K7 AND ~R7 OR ~Rd7 AND K7 AND R7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	~Rd7 AND K7 OR K7 AND R7 OR R7 AND ~Rd7	Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

      subi  r22,0x11    ; Subtract 0x11 from r22
      brne  noteq       ; Branch if r22<>0x11
      ...
noteq:
      nop               ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SUB Rd,Rr	Rd = Rd - Rr	0 <= d <= 31, 0 <= r <= 31	PC = PC + 1	000110rdddddrrrr

Description

Subtracts two registers and places the result in the destination register Rd.

Status Register and Boolean Formula

I	–
T	–
H	⇔	~Rd3 AND Rr3 OR Rr3 AND R3 OR R3 AND ~Rd3	Set if there was a borrow from bit 3; cleared otherwise.
S	⇔	N XOR V, for signed tests.
V	⇔	Rd7 AND ~Rr7 AND ~R7 OR ~Rd7 AND Rr7 AND R7	Set if two's complement overflow resulted from the operation; cleared otherwise.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	⇔	~Rd7 AND Rr7 OR Rr7 AND R7 OR R7 AND ~Rd7	Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.
R (Result)	R (Result) equals Rd after the operation.

Example:

      sub   r13,r12      ; Subtract r12 from r13
      brne  noteq        ; Branch if r12<>r13
      ...
noteq:
      nop                ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
SWAP Rd	R(7:4) ↔ Rd(3:0)	0 <= d <= 31	PC = PC + 1	1001010ddddd0010

Description

Swaps high and low nibbles in a register.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–
R (Result)	R (Result) equals Rd after the operation.

Example:

      inc   r1      ; Increment r1
      swap  r1      ; Swap high and low nibble of r1
      inc   r1      ; Increment high nibble of r1
      swap  r1      ; Swap back

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
TST Rd	Rd = Rd AND Rd	0 <= d <= 31	PC = PC + 1	001000dddddddddd

Description

Tests if a register is zero or negative. Performs a logical AND between a register and itself. The register will remain unchanged. (Equivalent to instruction AND Rd,Rd.)

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	⇔	N XOR V, for signed tests.
V	0	0	Cleared.
N	⇔	R7	Set if MSB of the result is set; cleared otherwise.
Z	⇔	~R7 AND ~R6 AND ~R5 AND ~R4 AND ~R3 AND ~R2 AND ~R1 AND ~R0	Set if the result is 0x00; cleared otherwise.
C	–
R (Result)	R (Result) equals Rd.

Example:

      tst   r0     ; Test r0
      breq  zero   ; Branch if r0=0
      ...
zero:
      nop          ; Branch destination (do nothing)

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
WDR	WD timer restart.	None	PC = PC + 1	1001010110101000

Description

This instruction resets the Watchdog Timer. This instruction must be executed within a limited time given by the WD prescaler. See the Watchdog Timer hardware specification.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Example:

      wdr  ; Reset watchdog timer

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	1
AVRxm	1
AVRxt	1
AVRrc	1

Operations:

Syntax:	Operation:	Operands:	Program Counter:	Opcode	Comment	Stack
XCH Z,Rd	DS(Z) ↔ Rd	0 <= d <= 31	PC = PC + 1	1001001rrrrr0100

Description

Exchanges one byte indirect between the register and data space.

The Z-Pointer Register is left unchanged by the operation. This instruction is especially suited for writing/reading status bits stored in SRAM.

Status Register (SREG) and Boolean Formula

I	–
T	–
H	–
S	–
V	–
N	–
Z	–
C	–

Words

1 (2 bytes)

Table Cycles

Name	Cycles
AVRe	N/A
AVRxm	2
AVRxt	N/A
AVRrc	N/A